Can cadence virtuoso bestarted in windows?
Dear sir, I want to use virtuoso in windows. But I didn't find the guided tutorial till now. Also I'm not sure whether cadence virtuoso can be used in winodws.Wish someone could help me! Thank you.
View ArticleCan cadence virtuoso bestarted in windows?
Dear sir, I want to use virtuoso in windows. But I didn't find the guided tutorial till now. Also I'm not sure whether cadence virtuoso can be used in winodws.Wish someone could help me! Thank you.
View ArticleIn which file/cellview are the CDF parameters are stored ?
Hi,I do have a cell with schematic, layout and symbol view.Both are checked in into our 3rd party revision control system (Cliosoft SOS).This cell has some CDF parameters I want to change via the CDF...
View ArticleOphaned .cdslck file with custom view type
Version info: IC6.1.8-64b.500.10.EHF7015I have created a custom view type but have a problem with orphaned .cdslck files. The custom view type launches my own external application with a GUI interface...
View ArticleMax value of signal in second cycle
I want to find the maximum value of the signal in a particular cycle. I was using a max function in skill, however, it finds the maximum signal in a complete waveform.Is there any way or through...
View ArticleHow should I modify the sigma value when i used the Cadence Monte Carlo
Hi,I am using Cadence 6.16 to design the circuit.I want to know how to modify the mismatch( sigma or std?) of the mosfet when i run the Monte Carlo Simulation. Because i wanna a large mismatch model,...
View ArticleAMS simulation IE (interface elements) for fast edges
Hi,while doing AMS simulations like SystemVerilog (with EEnet package) in Virtuoso I am stuck with a rise-time limit for my output signals.The IEs (interface elements) that are automatically put in...
View ArticleHow to create Metal resistor
Hi I write this script but its wrong some where please advice?///////////////////////////////////// LAYER DERIVATIONS AND OPERATIONS/////////////////////////////////////-----------------------------//...
View ArticleChanging single transistor instance parameters via SKILL
I have custom transistor compact models that have what amounts to a fail flag. The flag establishes a certain type of behavior for that one transistor when set to one. I would like to be able to set...
View ArticleModGen routing problem in Cadence Virtuoso
HelloI started to work with ModGen (Module Generator), I started the new experiment with simple differential pair transistors as you see from the picture. I followed the Cadence help to create the...
View ArticleNetlist Extraction
Dear all,Please help me to understand about "Netlist Extraction". I am a new beginner.Why do we need to perform " Netlist Extraction" in post-layout simulation?What is the purpose of this?Thank you...
View ArticleGray/Grey schematic for easier viewing of highlighted nets
Back in the days of Cadence 5 I could tap alt-G on the keyboard and my schematic would toggle into gray mode to more easily see and follow highlighted nets through the schematic hierarchy. For the life...
View ArticleHow to run Cadence Virtuoso using the terminal (VMware Workstation - CentOS)
Hi,In addition to running Virtuoso using the terminal, how can I open a schematic, a maestro, or a layout view using the terminal?
View ArticleDifferent files formats needed for a complete IC and package design and...
HI All,Can anyone please let me know what are the different files (and their formats / extensions) required in a PDK to run a complete IC design flow in Virtuoso starting from schematic design to...
View ArticleRe: Environment variables to source from $home/.cadence/dfII
Hi,Is there an environment that I can set to source file viva.ini from $HOME/.cadence/dfII/viva/viva.ini ? Everytime when I run Virtuoso Visualization and Analysis (VIVA), the software will create a...
View ArticleGetting/highlighting all input pins of a design in schematic
Hi,I am working on a huge schematic in virtuoso with lot of pins. I wanted to know if there is any way that I could highlight or get a list of all the input pins only in the design.Thanks,Sunny
View ArticleCopying layout from cell to other cell issue
Dear Sir / MadamI am trying to copy a layout from a cell to a different cell, the problem that only MOSFET are copied but non of the rout contacts as shown below. Also please see the error message I...
View ArticleGroup as parametric set is not working
I grouped it like this : And I expect 5 points and I get 3 points : what am I missing ?
View ArticleFinding gain of stage 1 in 2 stage opamp using stb analysis
Hi,I have a 2 stage opamp in a feedback configuration. I am running stability analysis to find loop gain, gain and phase margin of the opamp. How do I find the gain of stage 1 of the opamp. I see the...
View ArticleEMX integrated inside Virtuoso
Hi All, Can you please also let me know which version of Virtuoso has EMX integrated inside it ? I think EMX was acquired by Cadence a few months back and is integrated now without having to separately...
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