Hi,
for functional verification we started to model our cells and top-level blocks in SystemVerilog.
For logic signals we are using the "logic' datatype.
For the analog signals we are using the 'real' datatype.
If "logic" outputs are connected together, one can set all unused outputs hi-Z ("1'bz") and just have the one selected output drive the common output node.
But if "real" outputs are connected together, the interface elements (IE) are creating a voltage divider due to their finite output resistance.
The question is, if it is possible to declare a "real" output as high-Z or equivalent ?
And/or what is the better way to model "real-valued" parallel connected outputs ?
In my case I do have several DAC outputs in parallel. Each output has an internal transmission-gate to enable/disable the output. Only one DAC output is active at the time and drives/gives a "real" value to the output.
How to model this without getting a voltage divider due to parallel connection ?