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Switching threshold of ibis_buffer
I use the "ibis_buffer" component of analog Library "analogLib" to verify my IBIS model of a 3-state output buffer. The IBIS data is included by file. My testbench includes this ibis_buffer and the...
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How to control AMS waveform data compression
Hello,I am running a long top level AMS simulation, saving a lot of signals across multiple hierarchies. Most of the signals are used just for checking functionality, but on a few of them I want to to...
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Virtuoso DEF import creates incorrect pathseg widths
I have a DEF coming from ICC and when I import the wires do not get created at the correct widths. For instance, the DEF specifiesUNITS DISTANCE MICRONS 4000 ; + LAYER m2 WIDTH 104 SPACING 80But when...
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Incorrect multiplier in Spice In
Hi,I used Spice In to import SPICE netlist to generate schematic in IC181 (version ICADVM18.1-64b.500.4). The technology is in tsmcN16 and library is defined in cds.lib. Schematic was generated without...
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Metal Track does not show up
Dear all,When drawing a metal track, it just displays a line (even when I am changing the width of the track). See attached figure.Does somebody know how to solve it?Thanks.
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Send dc match results to the outputs
Hello everyone,,I wonder if there's a possibility of sending the results of a dc match simulation directly to the ADE-L outputs window. Typically, a summary of the dc match results can be seen in the...
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Layout GXL: Binder and master difference
Dear all,When I am flattening a transistor, adjusting some layers and consequently making a cell, I am getting an following XL status: "master difference, connectivity difference"I am doing the...
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Warning: Net “clk is not glued to any wire”
I have this Warning: Net “clk is not glued to any wire” and I dont know the cause of the problem.Can you help me with possible solutions?ThanksGenas
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Difference between Virtuoso_Acceler_Parallel_sc and...
Hi,For running simulation, Spectre typically uses licenses from Virtuoso_Multi_mode_Simulation pool. We have seen that with +mt=1, +aps license are picked up from Virtuoso_Acceler_Parallel_sc. What is...
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extend analog stop time
Hello, In the xrun.log file of one of my mixed signal simulations (ams simulation), I see one line"The analog simulator has reached stop time, please use 'analog -stop <new stop time>' to...
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Assura Failing during creating the schematic database
I have an auCdl view of a flash in my digital top schematic to use the cdl for the flash. We've had success running LVS when we export the entire schematic to a cdl using connect by name option....
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Usage of int and max functions while passing variables from parent schematic...
Hi,I've created a schematic and passing variables from higher level to lower level. I want to execute few commands before assigning values to parameters of devices. Let's say, I've a variable named X...
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Plotting transistor operating point components in DC simulation
Hello,I am using Cadence Virtuoso IC6.1.5-64 bit and ADE Spectre Version 11.1 2012I am trying to plot different operating point components of the MOS transistor (gm, region, vth,...etc). In my simple...
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Liberate : generate lib file for a level shift cell
Hi, Did anyone generate the lib file for a level shift with liberate? I don't know how to make some settings.(1) For the following netlist, .SUBCKT ls_cell IN OUT VDDH VDDL VSS*.PININFO IN:I OUT:O...
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Extract logic cells from design to match cells provided by pdk?
Hello,I'm completely new to this so please bear with me.If I'm provided with some standard cells, and would like to use a design that I have in an FPGA to port to an ASIC using the provided cells, how...
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tie jitter function
Hi,I wonder if there's function or expression based on existing functions to check tie type of jitter. To elaborate, the goal is to check corresponding edge difference from clk_sim (from simulation)...
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Import .mod file
Hi all,I am using IC6.1.8 version and trying to import the spice model of an external component; in the netlist there are only capacitors, inductors and resistors. I already did It in the past, but It...
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assura rcx fails
hello everyone,when I do the post-layout simulation of the inverter there is an error in RCx extraction, images of that error I also attached below. please resolve my problem.
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Running AC and DC simulation in the same time
Hello,I am trying to simulate the input common mode range of my operational amplifier using Cadence Virtuoso and spectre ADE.The simulation concept is to sweep the input common mode DC voltage (VIC)...
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ERROR (OSSHNL-402):
Hi,I'm trying to simulate a block's view generated by PEX (Calibre parastic extractor). The block is LVS clean, and it seems no issue when generating the post-layout view.I have followed the same...
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