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Voltus-Fi vpserro layers display
Hello everyone,I am currently adapting Voltus-Fi to the design flow (UMC180 technology).The EM/IR analysis through ADE-L seems to work (judging by changing the output plots).But displaying Results >...
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frequency dependent component
Hi,I want to incorporate some frequency dependent resistors and inductors for my AC simulations.People have recommended to use something called GLAPLACE but I have no idea where to find it and how to...
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Help with ADE XL simulation
Hello everyone,I am a starter of cadence and I came across an issue with simulation using ADE XL. When I copied variables from schematic in the cellview to the test editor of ADE XL, the following...
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Difference in "Voltus_Power_Integrity_Fi_L" && "Virtuoso_Power_System_XL"
Hi,When i am trying to use "Voltus-Fi" , it says failed to check out "Virtuoso_Power_System_XL" license. I have "Voltus_Power_Integrity_Fi_L" license with me. So, want to understand why it requires...
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Dynamic glitch check - on bus + variable level definition
Hello,1) Id like to create dynamic glitch check on multiple busses. Unfortunately when I select bus node for example "test<4:0>" the glitch check doesnt work. If I separate it by single wire:...
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display result from on-going simulation
Hi,In my case, I need to set output format to fsdb for spectre transient simulation. However, w. that change, I cannot load/update waveform while simulation is on-going, I can only do that after...
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How to do back annotation for wire RC extraction from layout to schematic
Hi,I am testing a simple circuit. There is a difference between post-layout simulation and schematic simulation due to parasitic R and C from wire. I subsititute RC from post-layout extraction into...
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tie jitter function
Hi,I wonder if there's function or expression based on existing functions to check tie type of jitter. To elaborate, the goal is to check corresponding edge difference from clk_sim (from simulation)...
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Full chip transistor level simulation convergence problem
Dear All, We are working on analog mixed signal chip design, already done AMS simulation, LEC on full logic. We would like to simulate the full chip with both analog and digital circuit in...
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ADE XL Error
Hello, ADE XL is complaining error about the level of metals from process.scs ERROR (SFE-1996): "/home/grps/ef-test/GLF8HP/130HPSIGE-8HP/V1.8_3.0HP/Models/Spectre/models//process.scs" 1236: Parameter...
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Installscape/Cadence Installation Questions
Hello,I have Cadence IC6.17 installed on Centos 6.I want to install further add ons to this version such as hotfixes for this version and also Incisive and Assura.My first question is,do I have to tell...
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Calibre xACT3D Extraction Speed Problem
Dear Sir/Madam, In PEX, we could speedup the processing time of extraction netlist by using "Multi-Threaded" or many of CPU to do. We found out the problem of placing the components in schematic....
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Which "efficient algorithm" uses ADE-XL for global optimization?
Hello,I am working on optimizing a design but the local optimization algorithms are not suffcient since possible solutions are not in the neighborhood of each other.That is why, I am using global...
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Liberate Characterization - Errors with encrypted PDK Model file
Hi I am trying to perform power and timing characterization on my custom cell designed and implemented in STM 28nm latest PDK.The problem is that the tool gets error when reading PDK model file due to...
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Liberate Characterization - Errors with encrypted PDK Model file
Hi I am trying to perform power and timing characterization on my custom cell designed and implemented in STM 28nm latest PDK. (Cadence Liberate version 16.1)The problem is that the tool gets error...
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How to pass LVS with shorted nets?
I have a bunch of nets which need to be shorted in my design. I am using the cds_thru to connect the nets in my schematic, and I have shorted those nets in my layout. I am using Calibre to check the...
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Mosaics with non-instance objects (e.g. vias)
Hi,is there a possibility to use the mosaic function or something comparable on non-instance objects, for example vias? What I want to achieve is that I can place an array of an object with a defined...
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Extracting a measurement from multiple spectre simulations
I'm running a simulation with multiple runs 500+. I'm only interested in the variations in voltage on a single node at a single point in time, say node 'out' at 200us.I used to know how to add a few...
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Spectre XPS MS post-layout simulation
Hi, We are designing a custom SRAM memory array, after extracting parasitics from layout (PEX) and trying to do post-layout simulation spectre needs too much time (1000hrs) if using aps++ mode....
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AMS Simulator Options to ignore supply nets verilog models of standard cells
I am trying to run a mixed analog and digital simulation that includes standard cells with HDL views. I can run all analog simulation fine, but I want to speed up and use the HDL view for the standard...
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