How to do back annotation for wire RC extraction from layout to schematic

Hi,

I am testing a simple circuit. There is a difference between post-layout simulation and schematic simulation due to parasitic R and C from wire. I subsititute RC from post-layout extraction into schematic with T model for wire. However, the back annotation on schematic doesn't show same simulation result as I have on post-layout simulation. I am confused about this part. Is my wire model here (L or T model) not correct? or I missed sth?

Could anybody help me with it?

Thanks,

Po