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Assura LVS not running
Hi,I am trying to do LVS on old design (a simple buffer), but LVS seems to be running indefinitely without displaying an error as below.When I view the log files (shown below), it does not seem that...
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emergency help!!! logic gates
first of all, I apologize for my poor EnglishI use a logic gate like or from tsmc18sc library and want to simulate it with pulse input. when I simulate it in tran modethe output is always zero
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Pnoise sim with different noise type
Hi,I try to study PNOISE currently, and the simple Res+MOS switch+Cap is my schematic.The switch Fs=1MHz, RES=10Kohm, CAP=1pF.I found that there are many noise type in PNOISE setting as follow...
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Liberate for library file
Hello, everyone! I have a problem with the usage of Liberate. The error information is *Warning* (write_verilog) : No function written for pin Q of cell balloon_sim_nogndThen, I look at the verilog...
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Assura DRC decks writing
Hi All, I'm New to this forum and very happy to join you all. I'm struggling in writing a rule deck in Assura which is already mentioned in Calibre. The rule/syntax in Calibre 1: ACT_HORIZONTAL_EDGES =...
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Pcell Evaluation Failed Issue
Hi,I have an issue, when I invoke the tool I am getting pcell Evaluation failed for all the cells coming from techlib.I am working in 10 nm and tech lib is cmos10lpp.What I did is I copied cmos10lpp...
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Jitter simulation, PSS +pnoise and matlab get different results
Jitter is obtained in two ways, both of which first simulate pnoise.The first one gets pnoise curve, pnoise at various points from 1k to 10M, and then puts this value in matlab.The second one is jitter...
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corner variables in adexl
If I have to add two variables in corner setup of ADEXL, is there a way to specify them as connected like ordered set. For e.g if var1 can take {10 20} and var2 {0 var1} -- so the net runs {var1 var2}...
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Job name in adexl and directory where it will be saved
When I start a new job in ADEXL, it is named "Interactive.nnn" etc. I cannot edit that name while the run is in progress. Most of times I come back later and cannot recollect what that run was for. Is...
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ADE-XL: possible to reuse Matlab-type outputs in other scalar outputs?
Hi! Is it possible in ADE-XL to have (scalar) outputs that take as input the values returned by Matlab-type outputs ("measurements")?For example: I have a Matlab output which calculates SNDR for an ADC...
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VerilogA Modelling for Skin Effect
Hi all,I'm trying to model skin effect using VerilogA. And I got the sample from Ken's website: https://designers-guide.org/modeling/ind.pdfHere's the model:`include "constants.vams"`include...
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Layout Suit L Editor: Transistors Properties and Pin Definition
Hello,I'm working with the TSMC 0.18um PDK for our Labs. I faced two problems which are new in this PDK for me against the X-Fab or AMS. I will be appreciated if anyone shares his/her experience...
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Virtuoso ADEXL VIVA Calculator Sum function?
Hi, This might be a dumb question; however, if I want to sum 100's of signals through the VIVA calculator is there an easy way to do it? I don't see a "sum" function. Thanks, PM
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calculator returns 0 for 1/2/3.14159
I am using IC6.1.7-64b.500.23I find a similar post on this forum, I am doing a similar...
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.cdsinit command for schematic pin/net collision setting
In .cdsenv there is a setting that checks for pin/netname collisions:schematic srcPinNetCollision cyclic "error"How can I set this in .cdsinit ?
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Layout: Cannot change terminal from scalar to bus
Hello everyone,I have a layout in which a scalar pin exists. Now I want to change this pin to a bus pin. But if I try this, I get the error Edit PropertiesCannot change terminal Name 'Vbb_lp6_PA' to...
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using the switch in the analoglib
Hello, i'm trying to use the ideal switch (relay) from cadencelib to create a 50MHz clock signal from a variable DC power supply. I have connected the relay with a vsource with the required frequency...
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noise/jitter analysis of CDR in cadence
Dear sir, I am designing a 5Gbs clock and data recovery using TSMC 0.18um library. I would like to generate an eye diagram and find p-p/rms jitter of my circuit. All of my circuits are using the TSMC...
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Simulating circuit on PSPICE Convergence error
I'm trying to simulate an one bit ADC using only mosfet transistors but keeps giving me an convergence errorThe model info for each of the transistors are .model MbreakP PMOS LEVEL 3+ TOX = 9E-9 COX =...
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how to set libmanager open automatically as ciw
Hi,Is there anyway to set libmanager open automatically as ciw when cadence is starting ?Thanks
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