Hi,
I have an issue, when I invoke the tool I am getting pcell Evaluation failed for all the cells coming from techlib.
I am working in 10 nm and tech lib is cmos10lpp.
What I did is I copied cmos10lpp folder from one path to another path (into my local) and I added my local path to cds.lib
Then I tried to invoke the virtuoso (V12.3-64.b) then if I tried to open the layouts all the cells pointing to cmos10lpp are getting pcell evaluation failed.
I re invoked the tool and attached the techlib also but same problem exists.
I opened the layout then in the verify ---> Markers --> Explain and then clicked on the layout then it is saying
location: ("cmos10lpp" "egpfet_b" "layout")
reason: ("eval" 0 t nil ("*Error* eval: undefined function" Secln10lpp_mosfet))
Can any one tell me the solution please.