how to update connectivity reference hierarchically
Hello,when I opened layout of "A" and launched layout XL, the schematic popped was of "B". I did update connectivity reference to schematic of "A". But, the whole hierarchy of "A" is having...
View ArticleLimited History Entries?
When trying to run more than 10 concurrent runs from a self-constructed OCEAN script, on the 11th run I encounter the following error:ERROR (ASSEMBLER-3015): The number of history items for which...
View ArticleEvaluate an expression once per Corner - ADE Explorer
I'm trying to measure the output resistance of my analog block. I vary the output bias voltage a small amount and record the current for each value of the bias. I then calculate the output resistance...
View ArticleSimulation crashed - Killed by user
This simulation suddenly crashed and there was a line saying that "Killed by user". I didn't kill it myself. Does this mean that someone actively killed it?
View ArticleIs there any shortcut, bindkey to bring up CIW window quickly?
Is there any shortcut, bindkey to bring up CIW window and Library Manager quickly?(version IC6.16-64b.101)
View ArticleLicense wait limit for schematic netlisting commands
Is there a way to specify that schematic netlisting commands using the "si" or "ocean" commands should internally queue for a license rather than exit with an error if the appropriate license is...
View ArticleParameterizing model section
I'm using a model library with multiple sections for different process corners, and would like to be able to flip between them with a variable in ADE-L, without resorting to ADE-XL. Is there a way I...
View Articlecustom marker layer
hello experts,wondering how can I add a couple more marker layer to identify our own custom pcell other than existing PDK layers? any quick hint or tutorial or reference would be greatly...
View ArticleWhich virtuoso version is more recent, IC 6.1.7-64b or IC 6.1.7.500.17 ?
Hi All,Which virtuoso version is more recent,IC 6.1.7-64b or IC 6.1.7.500.17 ? Because I have a problem in pcells, it wont change parameter.Best regards,Marben
View ArticleLibrary manager shows layout cell is checked out BUT there are no lock files...
Situation:User1 (mysefl) originally created the layout cell "test1".User2 has the cell checked out and the DesignSync Status Browser shows the version is in edit (version: 1.2->1.3).The Cadence...
View ArticleExporting the waveforms from Cadence ADE to plot it in Mathlab
Hello,I need your help please to export my waveform results from Cadence ADE simulator to plot it in Mathlab. Is that is possible?Thank you
View Articlelaunching ModGen in Cadence virtuoso Layout editor
Hello,can you tell me please how to run the Modgen in Cadence Layout tool? I tried to find it from different places in my simulator but I couldn't see it. Perhaps my simulator doesn't support this...
View ArticleCadence Liberate for characterizing
Recently, I use Cadence Liberate to characterize the standard cell. Some novel error occurs, shown as the followERROR reminder:Did anyone meet with this type error? Hope someone can help me!Thanks a lot!
View ArticleChange size of all the solder dots in the schematic
Is there a simple command to reduce the size of all the solder dots in schematic so that the schematic pic captured with "export image" look neater.
View ArticleVirtuoso 6.1.8 plotted expressions in VIVA do not fit to evaluated...
Hello,I encountered the following problem using cadence virtuoso IC6.1.8 ISR3 with SPECTRE 18.1 ISR6.I did an stb analysis with a global variable sweep ("temperature" and "L"). Furthermore, I created...
View Articlewhat is the difference between "parseAsCEL no" and "parseAsCEL don't use"?
subject says it all.
View ArticleUnable to run Spectre181 on Ubuntu16.04 -- GCC Version mismatch
Here is the output log (spoectre.out) when I try to run a transient simulation from ADE(L) in virtuoso. I initially wrote a d_ flip flop and applied a clock to the symbol of the d_flip_flop. Why do I...
View ArticlePhase Noise simulation accuracy
Hi,I am trying to simulate the phase noise of a clock receiver block. It is a complex block, but you can imagine as a cascade of various buffers which are biased by some other biasing blocks (which...
View ArticleIt seems auCdlPutMathExprInSingleQuotes only works for subckt netlister(like...
subject says it all.Thanks.Fred
View ArticleIs there a way to customize the netlist fom subckt netlister(like...
subject says it all.Thanks.Fred
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