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How to save Spectre tran results over just a specific period in a simulation
Hello,I am running a spectre simulation from the command line and, as my simulation is large and extracted, I'd like just to save the tran results over a certain period. Not for the whole simulation.My...
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QRC conflictiong name spaces
Hello,I'm trying to generate an extracted view from a layout with QRC and, after selecting the LVS run to be extracted, I'm promped with the following message:"You are about to enter names from...
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How to setup and simulate differential TDR
Hi,I want to do differential TDR simulation in cadence virtuoso. I have a differential channel, made of Tlines and interconnects (passive componenets). How to setup the TDR simulation to get impedance...
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ADE XL new test addition on a running simulation
How can I add a new test to an existing running ADE XL Simulation? Since it takes a couple of days to run the same I don't want to run it again , so if there is any possible ?
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Vgs exceeding in the PSS analysis
I am doing PSS analysis to calculate the THD. I ran the simulation for all blocks separately and everything is fine, but when I place then as a chain, I receive a Vgs exceeding warning. I checked...
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Transient DC voltage setup
Hi TeamI have attached 3 pictures concerning an issue of a spectre transient simulation. The first picture is what my test circuit looks like, which is in differential configuration. Each have 2 tones...
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Using the Navigator in Virtuoso L
Very simple question...When in Virtuoso L, using the navigator I can highlight a net that is open and needs to be routed. The problem is, as soon as I click in the layotu window the flight line goes...
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Difference between V(P1,T1)
Difference between V(P1,T1) <+ 0; and V(P1) <+ V(T1); in Verilog A I think V(P1, T1) <+ 0; would mean voltage difference between node P1 and node T1 is 0 and V(P1) <+ V(T1) would mean...
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ade explorer set instance value
hi,i create one simulation in ade assembler, several test for simulation, for example, i place one analoglib “port” in schematic, but different test need to set different port source type, like dc and...
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how to generate spectre netlist for all the schematics in 1 lib ?
Hi ,I would like to generate spectre netlists for all of the schematic cell in my lib. What can I do ? I search in the forum but didn't the answer yet thanks Nhumai
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Create a symbol from layout
I have created a symbol by momentum for a transformer in 65nm technologybut when i use mentioned symbol in a schematic and try to run LVS, but i have gotten error consider that the symbol could not...
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how to set a bindkey to display multiple layers ?
Hi, I am using cadence 6.1. I am trying to set a bindkey to display certain layers at 1 time. For example key '0' will display base layers, key'1' will display metal1 via2 and metal 2 . I have a simple...
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Export transient waveform into ASCI/CSV format for psfxl simulation data
I used to use the psf function $CDS_INSTALL_DIR/bin/psf to output transient waveform into an asci format. Is it possible to use the psf function to do do this on a psfxl transient data? If no, is there...
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Virtuoso L and virtuoso xl cost ?
Hi All,How much does Cadence Virtuoso L cost and Virtuoso XL cost ?Because I want to compare their prices.Best regards,Marben
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problem with resistor in corner analysis
hi i am designing a circuit (transimpedance amplifier ) that has a few resistors .. i want to do corner analysis and when i use resistors from tsmc library it gives errors and says that these resistors...
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How to use rand_bit_stream for trasimpedance amplifier ?
hi i need to simulate eye diagram with cadence 6.14 for my transimpedance amplifier .transimpedance amplifiers input is current. i know i should use rand_bit_stream from ahdllib for generating random...
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Strange problem when working with small currents in ADE L
Hi,I noticed a problem when simulating in ADE L with a 0.18um technology. For a simple current mirror, I found that results are not reliable for small currents (in the order of nA) if transistors’...
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Include CDF callback parameters in netlist
Dear All,I'm completing a test design using the gpdk045 and gm/ID methodology for educational purpose. For my technology generation (lookup tables of DC sweeps) I use the gm/ID starter kit scripts of...
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Preventing a stupid schematic mistake with NMOS back-gates
I have a question that I suspect is more of a pdk thing than a Cadence thing. A regular PMOS symbol in our TSMC 0.18um library has 4 terminals (D, G. S. BG). That's fine. A regular NMOS symbol also has...
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Monte Carlo for Verilog A based model file
Hi,I created a symbol using verilogA from 3 file which contains the defination for the other module, I created the following modification in the top level filemodule FET(Drain,Gate,Source,Sub);...
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