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set parameter in definition files of adexl but given error of variable not...
I want to vary some resistor/capacitor values in monte carlo simulation and hence write a definition file named mc.h to be included in adexl simulation.But the adexl will still request me to give...
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ADE-XL: possible to change binding of "Open Terminal" button (launch xterm)?
Hi! I recently switched from IC617 to ICADV12.2 (64b.500.5), and now when I press the "Open Terminal" button in ADE-XL (results tab), two strange things happen:1) It doesn't open the terminal on the...
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VPS-L: vsaplot can't find "design.info" file
I'm running VPS-L in batch mode (version IC617isr21). I can run an EM analysis and get valid text results. Then I run the "write_em_vsaplot_db" command (it runs without errors) and open "vsaplot"...
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ADE-XL: force re-evaluation of Matlab script edited outside Virtuoso
Hello! Is there a way to force ADE-XL to re-evaluate Matlab scripts? I always edit my scripts outside Virtuoso, and when I press the re-evaluate button in ADE-XL nothing changes and I get the following...
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Plotting across corners with internal sweep in maestro
Hi,I am running virtuoso 6.1.7 500.17. In my TB, I created a maestro view (my first one) and ran a simulation with the following corners for one...
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design kits for a new member in cadence
Dear Sir/Mme,I purchased cadence tools since two years and the system as cadence is running (2018) with no design kits no technology and they said it is generic, and I did apply for different...
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how to enable to show all the simulation warnings
Hi All,In the transient simulation, there are many warnings, but they are suppressed. Do you know where to turn ON the option to show all the warnings or a much bigger number (say 100 instead 5)? Only...
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Checking installation of PDK is correct
We are changing manufacturer from MOSIS to Europractice, so I changed my TSMC N65 pdk provided by mosis to the equivalent pdk provided by europractice. Since the installation process has several...
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Library Manager: .cdsenv / .cdsinit settings not taking effect
Hi! I am trying to enforce some Library Manager settings, but somehow they are not taking effect. For instance, I have added the following lines in my setup files:-In my...
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How do you generate a layout from schematic in Virtuoso IC 6.1.5?
I know how to generate a layout from schematic in icfb (IC 5.1) using the Tools -> Design Synthesis menu in the Schematics XL window.Unfortunately this menu does not seem to exist in the newer...
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fail to use VAR as 'tran' analysis parameter
Hi AllVirtuoso IC 6.1.7.500.18 is used.I am using the variable for the stop time of the transient simulation.Just putting VAR("tSim") in the stop time field.This method runs pretty well most of time,...
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CDF parameters reusing default value from veriloga
I have a veriloga model for cell 'mosfet_model', where I declared parameters such as:parameter real w = 2u;parameter real l = 0.5u;Then I create a schematic cell 'inverter' which instanciates a symbol...
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APS: better Hyperthreading ON or OFF on the machine?
Hi! We recently got some new servers, and IT asked if they should enable or disable Hyperthreading on them (which effectively doubles the number of cores available for simulation). In the past I've...
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Why does renaming a file on Cadence Virtuoso take so much time?
Hi,I have observed that renaming a file (like a cell view name/schematic) takes so much time on Virtuoso takes so much time even if I deselect Update Instances option. On the other hand, if I copy the...
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SDF back annotation in systemVerilog design using interfaces
I have a DUT which is encrypted netlist and .sdf file (normally we do functional and timing simulations with these inputs). I used interface feature in SystemVerilog so I don't define any port for the...
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I have a problem adding custom vias in IC 6
Hi,I used to do this many times in IC5 and it worked fine, but our company decided to switch to IC 6 for the new projects and I am stuck. The problem is adding the customized vias that are coming with...
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Multi-Voltage domain pin checks at schematic level
Hi all.I want to exploit the pin properties from the Create Pin Form (signal Type, Supply Sensitivity, and so on) in order to check if my domain and signal are consistent based on the name of the pin...
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save waveform to file during simulation
Hi,I'm trying to find a way to save waveform to a file while sim is running.I was able to find a few ocean scripts in this forum but I wonder if there's i.e.veriloga script that I can create a cell and...
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probing signal in av_extracted_RC
Hello,I'm trying to probe some internal signal nodes of an RC extracted circuit, searching for root cause of a DC offset.The simulation is a simple dcOp from ADE-L on a test bench defined by hierarchy...
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verilog-a model help
Hi,I am new to verilogA. I am looking for veriloga code that generates a text output whenever gate of any transistor pmos or nmos rises to a file.Satendra
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