Difference between V(P1,T1)

Difference between V(P1,T1) <+ 0; and V(P1) <+ V(T1); in Verilog A 

I think V(P1, T1) <+ 0; would mean voltage difference between node P1 and node T1 is 0 and 

V(P1) <+ V(T1) would mean potential difference between P1 to gnd is equal to T1 to gnd.

I feel these statements kind of means the same, but when I used these statements in 'if block' in 'Verilog A', use of each statement gives different results, can someone please explain what difference does it make between these statements.

Also, can we use these statements in an 'if block'?