Creating layout window when clicked on the custom menu in schematic
Hello all, I want to create a new layout window when in clicked on the menu that i have created and inserted in schematic window, Please help me to do this.I have searched on creating a layout window...
View ArticleUsing calcVal for calibrating a circuit using local sweeps
Hi,In maestro I am wanting to run a cal test which sweeps a local variable called IL. For each local sweep I obtain an output, let's say Vout. This will be done over process only (temp and voltage is...
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i want to do that kind of simulation with cadence, but i don't know how to do...
in the below screenshot, there are two signals are competing each other and i want to check the metastbility, so one of them are swept and the other is fixed that was done in hspice , however i want to...
View Articleslow vias arrays
Is there a way to tell the tool to quit trying to draw all the vias in my array as I copy or move them?If I create a large array say 1000x 12, then try to copy it, the layout hangs (assuming to draw...
View ArticleGood strategy to make ADE simulations fully producible?
Hi,often you change something (dspf filke, schematic, testbench, variable, etc,.) and some trouble begins. So one good method is to go back to the last setup that works. In ADE this is possible by...
View ArticleIC618 cannot find files to start
Hi all,I was trying to learn virtuoso through Cadence training, I used "Virtuoso Layout Design Basics vIC6.1.8/ICADVM20.1 (Online)" in Cadence training. With OS RHEL7.9, after downloading IC618 release...
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Error in series capacitor voltage sharing during spectre simulation
Hi all ！In my design, I used series capacitors for voltage sharing. Prior to this, I built the following schematic to verify the voltage sharing function of the series capacitors, but the simulation...
View ArticleRun transient with cmin option but applied to certain sub-circuits only?
Hi,I run schematic simulations, and see a dirty behavior if I use cmin=10f. So some nets are very sensitive to parasitic caps. Although the circuit is no high-speed circuit at all (so 10fF should not...
View ArticleQRC's av_extracted view is not showing any parasitic resistotrs and...
HiI am using UMC 65nm technology. DRC LVS,,QRC is running fine. After Run ->Assura Quantus QRC, I get the dialog box as well output is in av_extracted VIEW. Once I open the av_extracted view,I am...
View ArticleCadence Simulation
Hello all,How to add a hard drive in the place of the simulation folder. Using the Monte Carlo simulation, the data is generated of 200 GB. How to overcome the storage issue.Thank YouRegards,Upendra Ch
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Could not find netlist procedure: _spectreCap instance
Hi there,Thanks in advance for your kindly reply.While I have a spectre simulaiton, which include the "cap" instance form analoglib in my schematic.It shows the error message belowHowever, everything...
View ArticleNew versions of GENNUS and INNOVUS not running on CentOS 9
We recently upgraded from CentOS 7 to CentOS 9. IC618, SPECTRE, GENUS152 work fine. GENUS 211(Aug. 2023 version) and INNOVUS211(Aug. 2023 version) do not start. The output is given below. It is not...
View ArticleDifference in ADE variable expression evaluation with and without a...
Hello everyone,I'm using an "if else" statement inside the (local design) variable value in ADE Assembler. The expression is used to assign a string value to a corresponding integer value.The variable...
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How to Access Reliability Report in Reliability RAK
Hello Everyone,I'm still going through the RAK to learn about reliability analysis.My problem is that the reliability report is disabled (picture attached) even though I followed the steps described in...
View ArticleInput through .VEC file
Can we mention 2 Time Period in a single .vec file?I mean for the first 20 inputs I need a time period of 8ns, and for the remaining 20 inputs I need a time period of 0.125ns.Can we use period 8 and...
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why diffusion sharing not possible
Hi,Could someone explain why diffusion sharing isn't working as expected on the top row? Are there any tool limitations preventing the sharing of the drain and source between two devices in this...
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For rotation of any polygon in layout which is made by SKILL IDE
I have written a skill code as pcDefinePCell(list(ddGetObj("designFlow") "Four_leaf_1" "layout")cv= geGetWindowCellView()rodCreatePolygon(?cvId cv?layer list("M9" "drawing")?pts...
View ArticleDefining Verilog-A vector in the maestro view
Hi all, I've been assigned the task of replacing vectors defined in Verilog-A code with parameters. The aim is for these vectors to be used as inputs in the Maestro. To give you some context, here's...
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Best strategy for adding dummies for CC placement
Hi, Could someone provide guidance on the optimal strategy for incorporating dummy elements into this circuit? The layout pattern is common-centroid, and it's essential to maintain this configuration...
View Article[si netlister] not running, but no useful error message
Hi all,I'm running the "si" netlsiter and It's saying that I have successfully checked out the license and what the value of some timeout is.% si -batch -command si.cmd -cdslib ../../cds.libVirtuoso...
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