Clik here to view.
marknet highlight error
When highlighting with the marknet option in the layout, the net is highlighted on a blank screen where there is no layer.I have attached a screenshot of the error message in the body of this...
View ArticleADE - MATLAB Integration - get path of maestro cellview / store matlab...
Using the ADE - MATLAB Integration, matlab is started in the working directory of cadence.The Virtuoso working directory also becomes the MATLAB working directory.Placing multiple matlab scripts for...
View ArticleClik here to view.
ERROR: Simualtion issue on EMX
Hello all,When I am simulating the EMX. It is not able to RUN and the error/problem is shown in the below-attached image. Please look into it. Kindly reply If you know. It will be helpful in this...
View Articlesave ahdl variable option
Hi,In the save option of assembler, basic page, there is one option: select AHDL variable (saveahdlvars). Q1, if "selected" is chosen, how to define those selected variable in assembler?Q2, there two...
View Articlecheck instance binding layout Vs Schematic
I would like to check per instance the binding (XL compliancy) between Layout and Schematic.Function bndGetBoundObjects can be used for this purpose, like:foreach(insts cvId~>instaces...
View ArticleIs it possible to do transient simulation with and without transient noise in...
Hello, I want to do a transient simulation with and without transient noise.Is it possible to do these in one go?So, basically it is like config sweep, but for transient noise.
View ArticleMeasurements across montecarlo
Hi all,I'm using IC6.1.8 and within ADE-XL I'm trying to perform the usual ymin ymax etc. operations on the results of a montecarlo sim. I followed the same procedure used for the corners sims,...
View ArticleHow to display dc simulation result of bus as decimal number
Hi.I run dc simulation and one of my results is bus 8 bits and I didn't find how to convert it to number in result tab.I tried analog2Digital and numConv but it doesn't work.Thanks.
View ArticleDC sweep using different sweep variables in corners
Hi,I am trying to dc sweep different types of trim codes by putting them in corner runs.For example I set "TRIM" as a DC design variable and use it in the dc analysis sweep variable name, with a range...
View ArticleClik here to view.
Analog Lib Switch
I have a simple VIN voltage divider of two resistors, Rtop and Rbottom.VIN is rise from 0 to 5V.I want the output don’t pass 1V, mean when VIN>2V VOUT=1V. when VIN<2V, VOUT=0.5*VINHow to use...
View ArticleViVA : Save image issue
Hi,I run Assembler with 3 Tests, and do a plot all. Now I want to export a png file. It works, but if I select Multiple Files the Save button is grayed out.By default, I got multiple plots, like from...
View ArticleAssembler MC: When is combine button available?
Hi,I run MC at nominal and one more corner (T=125C), but I want the histograms for nom and this 2nd corner in one plot. I remember this is possible, but why is the button "Combine" grayed out?I also...
View ArticleRun plan: Can I edit Design Variable setting?
Hi,in a test I use calcVal for trimming, but in parts of my run plan I want ot edit this. But it looks that it is not possible, because it is grayed out.What I want is using calcVal with ?cornerName to...
View ArticleMinimum realizable capacitance in UMC180nm Technology
what is the minimum realizable capacitor in UMC 180nm technology?
View ArticleClik here to view.
What is currently the most straight-forward way to retrieve the metadata of a...
My usual work flow of logging simulation result is exporting to a .csv file, which captures the scalar value. Then, I can create visualizations in third-party tools such as matlab or python. What I...
View ArticleClik here to view.
how to measure eye diagram on a data signal triggered on a self-triggered clk...
Hi, there.I’m having some trouble using a clk signal rclk_2 section 1 to trigger another data signal vod_a2b2 section 2… The issue was, if I plot the non-triggered eye of rclk_2, the pos edge...
View ArticleAssembler: How to achieve a trimming with calcVal for a corner analysis, e.g....
Hi,I managed to implement a trimming with calcVal and using?&cornerName "Nominal" for Monte-Carlo. I need to trim at typ. T and Vdd, and it works great. However, next I want to create a setup for...
View ArticleClik here to view.
How to extract the junction capacitor in pmos capacitor??
I am chung-ang university student, I have a problems when I extract parasitic component pmos cap in layout PEX.This is physical structure of pmos cap, and that modeling schematic.When I run PEX in...
View ArticleNoise analysis of a TIA
Dear folks!I have made a verilogA behavioral model for a Transimpedance amplifier (TIA). It is a differential input and a differential output TIA configuration, with the inputs being I_inp and I_inn,...
View ArticleRun Quantus fails: depending on which account it is being used from
HelloI am a professor teaching a 4th-year course on VLSI design. This year, I added a new lab requiring parasitic extraction using QUANTUS. The lab experiment runs without any error if I run it from my...
View Article