How to extract the junction capacitor in pmos capacitor??

I am chung-ang university student, I have a problems when I extract parasitic component pmos cap in layout PEX.

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This is physical structure of pmos cap, and that modeling schematic.

When I run PEX in Layout, I think Cch_nw, and Cnw_ps (parasitic capaciors) aren't extracted, because when i extend N-Well layer (= I think Cnw_ps should be increased due to junction area increasing ), there is no change of PEX result.

Please let me know, How to I extract the junction capacitor like Cch_nw, and Cnw_ps in the Layout??