Is it possible to download the slides from online training?
Is it possible to download the slides from online training?
View ArticleProblem when following Quantus Transistor-Level T2: Parasitic Extraction...
Hello, I am following Quantus Transistor-Level T2: Parasitic Extraction Training.If I do not source QUANTUS.cshrc, I can launch Virtuoso.But after modifying QUANTUS.cshrc file and source it as per the...
View ArticleHow to remove components from the frequency spectrum
Hi,I have a signal and its spectrum and I would like to run dft and sndr/sfdr on it. However, I have a few spurs in the spectrum and would like to run the spectral analysis removing those spurs. Can I...
View ArticleIs there a way to batch convert one netname for all cells in a library to...
Is there a way to batch convert one netname for all cells in a library to another netname?Although I could realize by "replace" in schematic menu, it has remained "edit mode" for almost schematics...
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techLibName of a library accidentally changed
Hello, I got this message when opening a layout from a library.The layout can be open but I can barely see anything.The layer palette also shows layers that i do not recognize.I found that the...
View Articlemultipole stb probe as actimes
Hi,I need to simulate multiple stb simulation once based on several probes, which are in different locations since there are several loops. I would like to use actimes in tran simulation, eg., actime1...
View ArticleObserving PLL Phase Noise with hbnoise
Consider an integer-N type-2 PLL with reference of 50 MHz and output frequency of 2400 MHz (N=48) with no behavioral model for any of the blocks (VCO, PFD, CP, Divider,...), all designed with...
View ArticleAssura LVS shows "n_psub_StampErrorMult" error
I'm designing a PA layout in Virtuoso 6.1.8.-64bMy circuit contains mim capacitors, rphpoly_rf resistor along with 2V rf_NMOS and 2 Sporal_std_mu_x_20k. I get these errors when I place a second...
View ArticlePlot the results of only one test in ADE Assembler
Is there a way to plot the results of only one test in ADE Assembler? I run multiple test parallel, but I would like to go over the results one by one (I have to look into the waveforms as well) The...
View ArticleIgnoring error CMI-2420
I am currently trying to model a transfer function with just a zero (I know this is non-physical) using the SVCVS in analoglib - is there a way to ignore the following error?ERROR (CMI-2420): G3:...
View Articlehow i can set dcdampsol
Hi,I got waring in the sim log and propose to set dcdampsol = yes in the dc sim option. However, I can't find where to define this parameter. It seems not a cds env variable. Thanks for your info.
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ADEXL netlist genration error (ADEXL-5025）
Dear Andrew,I am using virtuoso IC6.1.8-64b.500.27. Now whenever I used ADEXL, it reports the following error.There are no problems when I used ADE-L, while it doesn't work for ADEXL.Could you please...
View Articledoes PAC sim cover transfer function on carrier itself
Hi,In a system that amplifies or attenuates input depending on the frequency and input is a single tone clock (no modulation), If the goal is to find out the transfer function from input to the...
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No DRC Error, still seeing the cross on the layers?
Hi,I ran the assura DRC and found no DRC errors. Why the layers still show me the crosses? Is my layout really error free? What is the meaning of these crosses and how to get rid of them?Thanks,Vishesh
View Articlecadence simulation in digital IC design
This is my entire programmodule fourbit_multi(a,b,c,clk);input [3:0]a,b;input clk;output [7:0]c;wire s1,s2,s3,s4,s7;wire s5;wire s6,s8,s9,s10;always@(posedge clk)twobit_multi...
View ArticleHow to simulate Large signal bandwidth of amplifier
Hello,I would like to ask you about how to simulate the large signal bandwidth of amplifier in cadence. I know the basic test that requires to sweep a large signal sinusoidal condition and record the...
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Plotting with corners as x-axis.
I basically want to represent the data in the result table, i.e., measurement vs corners, in a form of plot.I am expecting measurements as y-axis vs corners as x-axis.a few weeks ago I saw a...
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Adexl - max jobs not exceeding limit 100
I saved a job policy with max jobs 1000 and defined same in cdsinit. When simulation is fired and I check individual test job setup, it gets reverted to 100 but no change in command. I verified in...
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Maestro - customizing default ouptut save options
In general, I save only selected voltages & currents, and no other information to save disk space & time. For any new test, I have to customize settings again (from allpub). Is there a way to...
View ArticleHow to edit scs files. I want to add this equation ueff=u0*(sigma*pi)to the...
How to edit scs files. I want to add this equation ueff=u0*(sigma*pi)to the ne. scs file in bsim3v3
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