Consider an integer-N type-2 PLL with reference of 50 MHz and output frequency of 2400 MHz (N=48) with no behavioral model for any of the blocks (VCO, PFD, CP, Divider,...), all designed with PDK.
Usually selecting Oscillator and selecting oscillator nets with estimation of frequency works fine in analyses, however I personally have had issues to obtain the phase noise of the output of the PLL.
I believe in either pss or hb, since you have a reference clock, checking oscillator box would stop the simulation since it argues that you have a periodic signal (reference) which is inevitable in PLL simulation.
Therefore, it makes sense not to choose oscillator, but to choose the harmonic, in the case I mentioned the 50 MHz, and either have >=48 number of harmonics are maybe 2 tone in hb analysis and then hbnoise to obtain phase noise. Please keep in mind that VCO control voltage will have an input reference leak that would create spurs around 2.4 GHz with 50 MHz spacing.
I have tried both of them but in all cases, the simulation never converged (of course, I mean hb, or pss, when no oscillator has been selected), thus can anyone comment on if I took any steps wrong or any better way that I can do to obtain phase noise?
P.S. To get a sense of the PLL phase noise I used PhaseNoise function in the calculator but that requires so many cycles to be able to see close in phase noise.