Failed to open the GUI of Cadence Abstract Generator
When I started the Cadence Abstract Generator by typing `abstract` or `abstract &` in the terminal shell, the terminal failed to start graphic user interface.Can you give some suggestions over...
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STB Analysis: Invalid instance name
Hi all,The same error in this post: Spectre stability analysis with active device as probe - Custom IC Design - Cadence Technology Forums - Cadence CommunityI have a testbench where I run STB analysis...
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CIW save display information - unbale to get rid of this popup when closing ciw
I don't know why this popup appears. But I tried saving file & close it. It popups again when closing ciw. Please help.
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Adexl - interactive history does not display design variables
In interactive history, is there a way to view design variables like global ones? Right now, I check input.scs for design variables. It's good if we can have this feature to check from history list.
View ArticleLayout output pins changing the behaviour of extracted netlist
Greetings,I am using virtuoso IC6.1.7-64b.500.15 to build an array of programmable ring oscillators (RO). I am employing a mix of library digital cells and custom cells to do so, following a custom IC...
View ArticleSegmentation Fault (core dumped) when invoking INNOVUS211
Dear all, I am trying to run Innovus (v21.11 64bit) on Red Hat 7.9 Linux, the tool tries to run but ultimately a "segmentation fault (core dumped)" message appears. I get the same issue when trying to...
View ArticleBehavioral modelling using verilogA for a TIA
Hi folks!I am working on the behavioral model of a Transimpedance amplifier (TIA) using verilogA. As I am new to the world of behavioral modelling, I wish to get some questions clarified right away:1)...
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Did not find 'analogLib.res:symbol'.
I am using the Virtuoso File-Import-Spice to import a spice file as a schematic cellview. I have included the necessary device mapping, and the "resistor" is mapped to "res" correctly. However, SpiceIn...
View ArticleDesign and placement of hard macros
Hello,I am looking for documentation or demos to design and placement of hard macros.For example, in my design, I have several instantiations of a single block. I want to have similar placement and...
View ArticleConvolution function of two temporal signals in Cadence Verilog-A
Hi,I would like to know how to achieve convolution of two signals in time domain with verilog-a language.I can totally understand the convolution theory but it is hard to me to realize in verilog-a.May...
View ArticleADE Explorer Message 2110
Hi,I run ADE Assembler simulation long hours will get error message "ADE Explorer Message 2110".Could you know how to resolve this issue and setting ?Error message:ERROT(EXPLORER-2110). Cannot run...
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Automate color on plot in VIVA
After rearranging some traces into a window, sometimes I end up with two or more traces with the same color.Is there any way to automatically set up the color so each trace has its own color?If you...
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Simulating a circuit in an array
Hello, I want to simulate a circuit containing 10 cells arranged in a 1 dimensional array.Only 1 out of this 10 cells is turned on at a time.So, the other 9 cells are either turned off or modeled with...
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Digital signal overshoot and undershoot detection in Cadence
HelloI have tested the digital output of my fabricated chip. The practical measurement shows me overshoot and undershoot peaking behavioral when the digital output change from logic state to another as...
View Article[Pcell] How do I create a Label for a rodCreatePolygon - Function?
Hi guys,I need to create a label through coding/script in a Pcell.When I try to create a label for my polygon shape, the code is getting compiled without any errors, but the label does not appear....
View ArticleHow to acces leaf-instance of subsckt for use as probe?
Hi,This article https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000tt0rEAA describes how to use probes of metal resistors as probes for differential stability analysis.However, the...
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What does the cut pattern "farm" mean?
I can select it from the list but there's no information to find about it.It result in something like this (see below) but I find it very hard to predict to outcome of the via pattern
View ArticlePSS ANALYSİS
hello everyone,While I run post layout pss analysis for the divider (divide by 250), I get insufficient memory error. server ram is the 128G. I reduced PEX size to 10M but RAM is still not enough. I...
View ArticleRLC parasitic extraction type for post-layout simulation
Hello,I usually use RC parasitic extraction for my post layout simulation with Cadence Virtuoso tools. But I have seen the option of RLC extraction as well. I never used it because I am afraid it...
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Adexl - dynamically stop transient run on event trigger
I tried to use MDL control as mentioned in support link here. It works fine for event tigger but not for additonal 10us delay. Please help here.tran_autostop.mdl file contents: alias measurement...
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