Hello
I have tested the digital output of my fabricated chip. The practical measurement shows me overshoot and undershoot peaking behavioral when the digital output change from logic state to another as seen from the image below. The maginitude of these bouncing is sometimes high enough to unwillingly trigger the next connected digital parts.
I wonder why this over-and-undershoot was not predicted with Cadence Virtuoso when I run the transient simulation, the result was coming clean, may be with one peak at every step change and I use the conservative transient simulation.
Thank you in advance
Regards
