Spectre segmentation fault
Dear Cadence support,we encountered a problem with our new computing server (please see specs below) during Spectre simulation. When we use 64 GB (2x32 GB) RAM memory, spectre simulation is running...
View ArticleDisplay two area of a tran sim simultaneously?
Supposing one is interested in looking at a signal at two disparate areas of a transient sim, such as an output on both a rising and falling edge of a stimulus signal.Is it possible to have VIva...
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Assembler: Can't use VAR() in output expression when EvalType is sweeps, all...
Hi,I am trying to check some output expressions with evaltype set to sweeps. In these expressions, I have some variables from my global variables. For the run, I am sweeping some variables and some of...
View Articlehow to input hex to a 32bit bus pin
Hi,A block has a 32bit input pin A<31:0>. I know what the setting needs to be but there is only VSS, VDD in the testbench, to write such expression is both tedious and error-prone. I wonder if...
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Can I hide the gray rows in output results table?
Hi, after MC, in Detailed-mode results table, I applied a filter to see only the critical samples. But the result is not easy to read:So I many columns which show no useful information, even not any...
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Cadence Viva - customizing traceLegend font size
Customizing traceLegend font size is not working for me both from envSetVal & Graph Properties. It's fixed to 9 only. Please help.Virtuoso sub-version IC6.1.8-64b.500.26 (64-bit...
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single-sided vs double-sided noise in noise upconversion
I have a question about noise upconversion. I multiplied a 50MHz sinusoidal signal of DC=0 and amplitude=1V by a noise source created by two noise/freq pairs of a DC=0...
View ArticleADE Assembler: Strange corner GUI observations
Hi,in Run Summary assitant I can see if corners are enabled, and how many. I remember in the past I could click to the checkbox and enable/disable all corners from here. However, in my current work...
View ArticleADE maestro results table: How can I filter out empty cells?
Hi,I want to see only outputs with specifications, but using a filter does not work for me.I can use the sorting feature as workaround, and make a screenshot. But for csv export I would still have...
View ArticleSome infuriating schematic capture "features"
Some infuriating"features" of schematic capture.1) When in a lower block in the hierarchy, and you want to select output(s) with the tedious "ADE_explorer>setup>select on design>outputs to be...
View Articleprogramable pattern generator
I wanted to check if some one has written a verilogA model for a patter generator, we are trying to develop a verilogA block which can generate NRZ, Clock, PAM4 pattern, take input from a file and also...
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Adexl Interactive - disable appending number to already renamed job
I rename jobs before start of the simulation using envSetVal("adexl.historyNamePrefix" "showNameHistoryForm" 'boolean t)But, tool will still append .0 .1 .2 like numbers to it. I have to wait for run...
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Schematic Navigator - cell list hierarchy is displaying like flattened post...
Sometime Schematic Navigator behaves differently by displaying cells in flattened post layout format. When clicked on any cell or net, it will not highlight in navigator. This will be very difficult to...
View ArticleAdexl - auto locking Interactive when run finishes
Is there a way to auto-lock the Interactive history when the Adexl job is completed?
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NO CC in PEX for fringe capacitance (the same as MOM)
Hi, I'm trying to get the capacitance of two pieces of top metal( noted as n<1> and p<1>) as follows. Here are several issues that confused me.1. I couldn't get the CC between n<1>...
View ArticlePost Layout Netlist - does order of devices and parasitic caps matter for...
Av_extracted post layout netlist has instance & devices definitions at the top. Parasitic caps at the bottom within subckt ends. My question is does order of parasitic caps in polo netlist matter...
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CAN THE DIFFUSION REGION EXCEED THE PR BOUNDARY IN HEIGHT?
I am trying to design a CMOS inverter. I have taken the PR boundary length as 1.52u. When I add my diffusion regions for both NMOS and PMOS, it exceeds the PR boundary at the top and bottom as the...
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Adexl Reference Netlist - new runs still point to old netlist even with...
I used reference netlist only (not results) for editing netlist and fired few runs. Later I disabled it, clearned Interactive name and fired new runs. But, the new runs are still pointing to old...
View ArticleWhat are the noise options under simulator options?
IN ADE_XL, using spectre, under simulator options, there is an options to turn on/off different types of noise contributions for different instancesCan someone give some explanation as to how to use...
View ArticleKind of tkdiff on schematics?
Hi,can we compare two schematics in Virtuoso, e.g. to see which transistors are missing in one, or which parameters have changed?Bye Stephan
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