How to see and get rid of design variables attached to cell schematic?
Hi,having such variables in a testbench is good, but accidently I have them also in my DUT circuit schematic. No in LVS the layouters are bothered with this and need to remove them manually in CDF.I...
View Articlevirtguoso layout non-exsist file list in hierarchy
HII try to convert library name and cells..I want to know losing cells in layout In schematic, I used Tree and I was able to find missing cells through "unbound"Is there way to find missing cells in...
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why i have such a pop-up window when editing symbol
Hi,I got such a pop-up window when finishing symbol editing, which didn't happen before. My virtuoso version is IC618-64bit.500.24Is there any env variable is changed ?
View Articlehow to use the random function in schematic?
Hi The following function abRandomNormal had been defined in ciw and it works. However, when give abRandomNormal() as a value to resistor in analogLib, in the simulation, it reports the following...
View Articlewhile simulating counter i got an error
ncsim: *F,NOLICN: Unable to checkout license for the simulation. Use ncsim -MESSAGES for more information. (flag - 2) 'lic_error -15'.
View Articlewhile compiling counter program i got an error
ncvlog: *E,EXPMPA (/home/cadence/counter4/counter4.v,1|9): expecting the keyword 'module', 'macromodule' or 'primitive'[A.1].
View Articlewhile compiling i got an error
ncvlog: *E,EXPMPA (/home/cadence/counter4/counter4.v,1|9): expecting the keyword 'module', 'macromodule' or 'primitive'[A.1].
View ArticleCan I set the order for the statistical parameter box in MC histograms?
Hi,the histogram plots show a little box in which important statistical data is shown like mean, stddev, skewness, kurtosis, and Jarque-Bera value. However, if you zoom out, then the content is cut,...
View ArticleDC and STB analysis reuse in larger sweeps
Hi,I have observed that running a DC but especially STB analysis will provide different results, depending on whether it is part of a larger PVT sweep or singled out corners.When running larger sweeps,...
View ArticleError during snapshots launch simulator
By selecting test module in snapshots for simulating the fulladder program , I have the follwing...
View Articlestb analysis after tran -any options required?
To use the final operating points in a tran sim as the basis for an stb analysis, is it as simple as making sure the tran analysis is placed above the stb analysis in Explorer? Do I need to fiddle...
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Integrate IC618 with FreePDK45
Hello, I am setting up tools for a couruse now. I have followed steps to set up IC618 base and FreePDK45. The OS is Rocky Linux 8.6. However, I have no way to make the layout display work. I can only...
View ArticleWhy does simvision sometimes causes the desktop freezed?
Why does simvision sometimes causes the desktop freezed?Below are some details,1. OS: CentOS 7.92. sivision version: XCELIUM/22.03.004When the simvision causes the desktop freezed, I killed simvision...
View ArticleSimulation on design series
I have a design with many versions. For example, my design with version number is mydesign_01, mydesign_02, ......, mydesign_99I'd like to run a same simulation on all of the designs. Is there a way to...
View ArticleMaximum value achieved
During DC simulation of an NMOS tsmc40 on IC618, I got number of warning and notices. One of the warning is " maximum value achieved for for any signal of each quantity: V; V(I0, Q) = 902.1 mv, I;...
View ArticleSet ViVa subwindow size using SKILL
How to set the subwindows custom array shape, i.e. 2x2, 3x10, etc. and set the size of each subwindow using SKILL?
View ArticleMaestro expressions in yellow
Hi, i see this post here, and i am having the same problemIs there an update on this?output setup shows a yellow row - Custom IC Design - Cadence Technology Forums - Cadence Community
View Articlefix RC corner
when I loaded data(RAC file from cadence) the error received as " **ERROR: (TCLCMD-995):Can not open file '../captable/t018s6mlv.capTbl' for RC corner ".
View ArticleHow to get all blocking layers touching a Pcell from inside Pcell code
HiI am writting a Pcell and want to avoid adding metal under routing blockages. The routing blockages are at the same hierarchy as the Pcell, and are not generated "inside" the pcell. I am having a...
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Override a VerilogA parameters module while in tran Analysis.
Hi EveryoneI Want to change 3 parameters in-sided a Verilog A module while in tran Analysis this change is triggered by the cross event every time the voltage across 0V.my parameter's new values are...
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