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APS and XPS MS encountered a critical error during simulation
Hello! Recently, I wanted to simulate a SAR ADC using APS. The settings are as following:But when I run it, an error occurred:I don't know what happened. It just said it was an "internal error".When I...
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AMS simulation fails to generate netlist
Hello,I recently performed AMS simulation. When I went to the last step, the following error occurred in generate netlist, I would like to ask if anyone hows to get rid of this error? Hope someone can...
View ArticleDigital components library for CMOSP18 in IC6 or IC5 in transistor level
Hi,I am trying to design a digital logic with some AND, OR, NOT, and DFF components. I am wondering if you could help me to figure out whether there are any libraries for CMOSP18 including these gates...
View ArticleSpectre failed to complete the simulation with Error ID=5011
Hello,I am running a post layout simulation by providing a SPICE post layout netlist (in a config view). I am running my simulation with spectre version 15.1.0.257 (64-bit).The job is running for a...
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SystemVerilog Outputs Incorrect Real Datatype Number Precision
Hello, I am using Virtuoso IC6.1.8-64b.500.23, Spectre 21.1.0.303.isr5, and Xcelium 21.09-s005 with AMS simulator. I have a simple SystemVerilog code as shown below to test output precision:module...
View ArticleDescribe the peak current method [Verilog-A]
Hi all I have a question about the current behavior.How to describe the peak current?For example, we have an inverter (A->Y); when the input value (A) rising to the Vth of the inverter, the...
View ArticleWhat is the correct way to make a cellview from DSPF file?
The DSPF textfile is created through the extraction.Then, I created the DSPF cellview and a text editor is opened.I tried using ctrl+a ctrl+c ctrl+v but it does not work.Trying to copy some part of the...
View ArticleHow to set appropriate transient simulation step size?
Hi guys, I've always seen suggestions in this Forum that it is necessary to set a specific minstep and maxstep when doing transient simulation. This kind of setting will make sure convergence. And I...
View ArticleWhat the license is required in spectre simulation?
Hi Senior user,What the license is required in the spectre simulation? Can I run the simulations without ADE license?I found below in the Support. Dose this mean if I can prepare input.scs file, I can...
View Articleextracting simulation temperature
Hi,I want to create an output expression for transient simulation in Assembler. Part of the expression has to be the simulation temperature. Since I will be running simulations for different...
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Using the same output expressions for post-layout simulation
Previously, I worked on smaller circuits and never had any need to probe inner nodes, just characterized the circuit performance from the output pins.Now, I want to probe inner nodes and use the same...
View ArticleOutput expressions from Data Browser VIVA vs. Calculator
We can get output expressions either from Data Browser in VIVA or from Calculator.They have different syntax.Data Browser : v("/ITOP/ILVL1/ILVL2/NVOUT" ?result "tran")Calculator :...
View ArticleHow to change pin size in an existing symbol?
Hi,in all my symbols, and also in analogLib, we have pins drawn as a small red rectangle. However, a more beautiful solution would be to have even smaller rectangles, like 25% of the standard size. By...
View ArticleGravity snapping through hierarchy
I notice that gravity seems to snap at the current or below current hierarchy level, but not above the current level. Is there an obscure setting somewhere to allow snapping to objects above the...
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ADE Explorer Checks/Asserts Skip Device Inside Subckt is giving an error
Hello, I am using Virtuoso IC6.1.8-64b.500.23, Spectre 21.1.0.303.isr5, and Xcelium 21.09-s005 with AMS simulator.I want to perform a device check on all devices on the current hierarchy view in my...
View ArticleThe cell is getting skipped during cell characterization
I've been trying to perform cell characterization for a basic inverter and generate a .lib file for it. But the cell keeps getting skipped during the processchar.tcl:set rundir $env(PWD) exec mkdir -p...
View ArticleParameter 'ad' not found in transistor models
I was trying to perform some cell characterization in liberate and I encountered this error:*Error* (char_library) : Failed to find parameter : adERROR (LIB-507): (char_library): Failed to process the...
View ArticlePin type options in Cadence Virtuoso
Hello,I have a question about the options for creating pins in Cadence virtuoso, there are many types to select, for example, power, ground, signal, clock ..etc.Do they have physical meaning during the...
View ArticleParallel routing from bus on the layout
HelloI am using Cadence Virtuoso version IC6.1.8-64b.500.6.I want to rout parallel wires from a group of bus pins on the layout. I tried to select those pins but when I do the Creat > wire > bus...
View ArticleInstance within a cell as parameter
I have a hard time describing what I want in few words, which also makes it very hard to search for it.I have a base-cell that already contains a number of subcells. To this cell I also need to add a...
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