SystemVerilog Outputs Incorrect Real Datatype Number Precision

Hello, 

I am using Virtuoso IC6.1.8-64b.500.23, Spectre 21.1.0.303.isr5, and Xcelium 21.09-s005 with AMS simulator. 

I have a simple SystemVerilog code as shown below to test output precision:

module test_blk1 (out1, out2 );
    output real out1, out2;
    assign out1 = 0.1;
    assign out2 = 0.0001;
endmodule

On simulating this with AMS simulator in a schematic view as shown below, the output of out1 is correct while out2 is zero!

Why is the "real - 64bit" precision not presented correctly in Virtuoso?

Any help is much appreciated.

Kindest Regards

Nader Fathy