Describe the peak current method [Verilog-A]

Hi all 

I have a question about the current behavior.

How to describe the peak current?

For example, we have an inverter (A->Y); when the input value (A) rising to the Vth of the inverter, the nmos/pmos will be open. Consequently, a current flow to ground.

The solution i found is that: 

-----code-----

if(V(A) > Vth) begin 

I(vdd) <+ 2.5uA;

end

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is it right? is it weird?

Furthermore, the peak current decided from the  circuit which peak in different moment and value.

So, is there have suitable way to describe the current peak in verilog-A logic ? really thank you!!