I've been trying to perform cell characterization for a basic inverter and generate a .lib file for it. But the cell keeps getting skipped during the process
char.tcl:
set rundir $env(PWD)
exec mkdir -p ${rundir}/LDB
exec mkdir -p ${rundir}/LIBRARY
exec mkdir -p ${rundir}/DATASHEET
set_operating_condition -voltage 0.3 -temp 40
set spicefiles $rundir/include_tt.sp
source ${rundir}/template.tcl
foreach cell $cells {
lappend spicefiles ${rundir}/NETLIST/${cell}.scs
}
read_spice $spicefiles
read_spice -format spectre ${spicefiles}
char_library -auto_index -ccs -ecsm -cells ${cells} -thread 4
write_ldb ${rundir}/LDB/Inv.ldb
write_library -overwrite ${rundir}/LIBRARY/Inv.lib
write_datasheet -format text ${rundir}/DATASHEET/Inv.txt
write_verilog -specparams -table_style min-avg-max -cells ${cells}
template.tcl:
set_var slew_lower_rise 0.1
set_var slew_upper_rise 0.9
set_var slew_lower_fall 0.1
set_var slew_upper_fall 0.9
set_var measure_slew_lower_rise 0.1
set_var measure_slew_upper_rise 0.9
set_var measure_slew_lower_fall 0.1
set_var measure_slew_upper_fall 0.9
set_var parse_ignore_duplicate_subckt 1
set_var max_transition 10e-09
set cells { Inv }
define_template -type delay \
-index_1 {0.250 0.500 0.750 1.250 1.500} \
-index_2 {0.0150 0.0500 0.1500 0.3000 0.6000} \
delay_template_5x5
define_template -type power \
-index_1 {0.250 0.500 0.750 1.250 1.500} \
-index_2 {0.0150 0.0500 0.1500 0.3000 0.6000} \
power_template_5x5
define_template -type constraint \
-index_1 {0.250 0.750 1.500} \
-index_2 {0.250 0.750 1.500} \
constraint_template_3x3
if {[ALAPI_active_cell "Inv"]} {
set inputs {D A B IN}
set outputs {Q QN Y OUT}
set clocks {CK}
set asyncs {RN}
define_cell \
-input $inputs -output $outputs -clock $clocks -async $asyncs \
-constraint constraint_template_3x3 \
-delay delay_template_5x5 \
-power power_template_5x5 \
Inv
}
include_tt.sp:
**
.LIB '/home/chips/55nm/umc55lp/SubVt/Inv_test/foundary.scs'
simulator lang=spectre
output:
Building library database
Processing cell: Inv
WARNING (LIB-519): (char_library): The pin 'Vin' is not defined for cell 'Inv'. Check the netlist and make sure it is consistent with 'define_cell' command.
WARNING (LIB-519): (char_library): The pin 'Vout' is not defined for cell 'Inv'. Check the netlist and make sure it is consistent with 'define_cell' command.
WARNING (LIB-519): (char_library): The pin 'A' is not defined for cell 'Inv'. Check the netlist and make sure it is consistent with 'define_cell' command.
WARNING (LIB-519): (char_library): The pin 'B' is not defined for cell 'Inv'. Check the netlist and make sure it is consistent with 'define_cell' command.
WARNING (LIB-519): (char_library): The pin 'CK' is not defined for cell 'Inv'. Check the netlist and make sure it is consistent with 'define_cell' command.
WARNING (LIB-519): (char_library): The pin 'D' is not defined for cell 'Inv'. Check the netlist and make sure it is consistent with 'define_cell' command.
WARNING (LIB-519): (char_library): The pin 'IN' is not defined for cell 'Inv'. Check the netlist and make sure it is consistent with 'define_cell' command.
WARNING (LIB-519): (char_library): The pin 'OUT' is not defined for cell 'Inv'. Check the netlist and make sure it is consistent with 'define_cell' command.
WARNING (LIB-519): (char_library): The pin 'Q' is not defined for cell 'Inv'. Check the netlist and make sure it is consistent with 'define_cell' command.
WARNING (LIB-519): (char_library): The pin 'QN' is not defined for cell 'Inv'. Check the netlist and make sure it is consistent with 'define_cell' command.
WARNING (LIB-519): (char_library): The pin 'RN' is not defined for cell 'Inv'. Check the netlist and make sure it is consistent with 'define_cell' command.
WARNING (LIB-519): (char_library): The pin 'Y' is not defined for cell 'Inv'. Check the netlist and make sure it is consistent with 'define_cell' command.
*Error* (char_library) : Failed to find parameter : ad
ERROR (LIB-507): (char_library): Failed to process the model based element inst: 'PM0', model: 'MOS' in the cell Inv. This cell will be skipped. Check the model uses standard parameter names and the define_leafcell command options are used properly. Update the Tcl script and rerun.
ERROR (LIB-203): (char_library): Cell 'Inv' is scheduled for characterization but has no netlist, has an empty subckt or has no port on the subckt. This cell will be skipped. Check the netlist and rerun.
---------- Entering compute template index ------------ Apr 16 06:18:20
Apr 16 06:18:20 Determining template indices...
WARNING: Unable to determine minimum load, using 1e-18 F
WARNING: Unable to determine minimum slew, using 10ps
Minimum transition index for the library: 1e-12 sec
Maximum transition index for the library: 1e-08 sec
Minimum output capacitance index for the library: 1e-18 F
Apr 16 06:18:20 Autoindex finished.
---------- Exiting compute template index ------------ Apr 16 06:18:20
WARNING (LIB-961): (char_library): Leakage deck initialization was requested using '.ic', but the 'leakage_sim_duration' was set to '0'. This may lead to unexpected leakage characterization results. Change 'leakage_sim_duration' to a positive non-zero value in seconds or change the setting of 'set_sim_init_condition' and rerun.
MEM=453 MB
MEM=453 MB
MEM=453 MB
*Info* (char_library) : SKI process child signal handler disabled.
MEM=483 MB
Performance statistics (4 thread(s)):
Spectre CPU time: 0.00 hours (0.00 seconds)
Total PreProcessing time: 0.00 hours (0.00 seconds)
Total cpu time: 0.00 hours (0.00 seconds)
Wall clock time: 0.00 hours (0.00 seconds)
Characterization finished at Sat Apr 16 06:18:20 2022
Characterization statistics:
Number of cells to characterize = 1
Number of define_cell commands = 1
Number of passing cells = 0
Number of failing cells = 0
List of failing cells {}
Number of skipped cells = 1
List of skipped cells {Inv}
Finished Liberate Execution.
Updating library database /home/chips/55nm/umc55lp/SubVt/Inv_test/LDB/Inv.ldb.2.gz
Memory usage: 482 Mbytes
LIBERATE parameter "mx_format_expand_buses" set to "0"
LIBERATE parameter "ecsm_multi_stage_cap_mode" set to "0"
LIBERATE parameter "ccsp_mode" set to "0"
WARNING (LIB-989): (write_library): This command will be skipped because there is no cell data to write. Characterize or read the cell data and rerun.
Writing datasheet in text format to /home/chips/55nm/umc55lp/SubVt/Inv_test/DATASHEET/Inv.txt.txt
*Error* (write_datasheet) : No cell groups found in the library /home/chips/55nm/umc55lp/SubVt/Inv_test/DATASHEET/Inv.txt
no value given for parameter "verilog_filename" (use -help for full usage) :
verilog_filename string () Output Verilog filename
while executing
"OptDoOne descriptions state arguments"
(procedure "OptDoAll" line 30)
invoked from within
"OptDoAll desc arglist"
(procedure "::tcl::OptKeyParse" line 10)
invoked from within
"::tcl::OptKeyParse write_verilog $args"
(procedure "write_verilog" line 1)
invoked from within
"write_verilog -specparams -table_style min-avg-max -cells ${cells}"
(file "/home/chips/55nm/umc55lp/SubVt/Inv_test/char.tcl" line 46)
Peak memory usage: 484 MB
Peak virtual memory usage: 407 MB
Peak physical memory usage: 79 MB
Wall time : 0.00 hours (4.00 seconds)
LIBERATE exited on chips-server at Sat Apr 16 06:18:20 2022