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Strange sharp rise/fall in stb phase plot
Hi Everyone, when simulating the amplifiers that includ current mirror load (diode bias+ current souce), I often meet a strange stb phase plot (figure below):Sometimes phase rises sharply and sometimes...
View Articlehow to set flight line that is just indicating the connections about the node...
For example..(1) I point a node, and then hit any key(2) Colorful lines fly to all the nodes connected to it (It's not actual wire..it only show the connection info) : "flight line"(3) I point another...
View ArticleConditional netlisting of instance depending on CDF parameter value
Hi,I've created a custom dcapĀ PCELL which depending on a parameter value will add a parallel MOSCAP for max cap density or a custom min dummy structure with the intention of minimizing parasitics to...
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Exporting several DC sweeps (OP transistor params) to CSV in an organized way
Hi,I'm doing a DC sweep on a single transistor. I also would like to sweep the lengths and widths.I have solution for now, but it's highly unsatisfactory, so I would like to be able to exhaust all the...
View ArticlePin size on CMOS circuit layout design
Hello,I would like to ask you about the criteria of making the size of the pins in the layout design, mainly asking about the supply rails (VDD, GND).I see from the IPs provided by the company they are...
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Transient plot of broken asserts
Hi all.I am usingĀ IC6.1.8-64b.500.10.I have table with asserts which is generated using asserts .scs file:Navigating to to schematic for a device that is causing break of assert works by clicking on a...
View ArticleSaving more parameters of MOSFET during transient simulation
Hi all.I am usingĀ IC6.1.8-64b.500.10.For DC sweeps I can enlarge list of saved parameters for specific MOSFET by creating .scs file and adding it to definition files.Content of mentioned .scs file may...
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How cadence generate the "IP Design.XML" file?
When i use Medini Analyze software to calculate the chip failure rate, it's support the IP Design.XML file import, IP Design.XML file include the DIE size information.So, i want to know, how to use...
View ArticleMultipart Path Dependent Separation and Multiple Master Paths
I'm generating some multipart path templates for shielding and I'm trying to figure out how to implement two functionalities that I don't see in the documentation.1) The separation for an enclosure...
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Where can I find the meaning of each parameter of the DC operating point?
I am learning cadence virtuosuo recently.I installed a tsmc0.18um process library.When performing simulations, it is often necessary toprint dc operating points.LIke thisļ¼ļ¼Q2 is a npn of tsmc0.18um...
View ArticleDFT expression results each in separate subwindow in ADE Assembler
I have 20 or so DFT expressions that all plot in the same subwindow when I use ADE Explorer. This is handy to quickly compare the magnitude of each.When I switch to ADE Assembler, each is plotted in...
View ArticleHow to resurrect Virtuoso schematic and export
I have Virtuoso schematics of a "digital" design (down to transistor level) I created 10 years ago, and last looked at 5 years ago. That represents the only times I've tried to run Virtuoso in the last...
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Updated Resistor Parameters Not Displayed
Hi All,When I update the W, L parameter for any resistor in my schematic it still displays the default or the previous value which is present. This problem is resolved only when I restart cadence and...
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missing some runs during monte carlo simulation
There are some runs that are missing during monte carlo simulation but if I re-run those specific runs, the results are there.I am usingĀ IC6.1.7-64b.500.15 Is there any setup that I missed?This is an...
View ArticleHow to query the Assembler results database for an evaluated expression?
An ADE Assembler window is open with one or more tests that are defined and enabled. The simulation has been run and the results tab shows a wave icon for each of the outputs. At this point I want to...
View ArticleWhat's the meaning of "9"?
Hi professionals,This is from spectre.out log.What's the meaning of "9" in below? It seems there is not the node9(or port 9) in the schematic...Matrix is singular (detected at `I1.I2.I3.I4.I5:9' and...
View ArticleHow to delete all ghost layers outside the visible bbox in Virtuoso Layout?
Hi all.Does anyone have a SKILL code or method to delete ghost layers that are not visible inĀ Virtuoso Layout?Why does it happen?Thanks.Jorge
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dcblock capacitor
Hi Allthe dcblock capacitor in the analogLib shows that the capacitance used in tran is 1u. What would be the capacitance used in s-parameter simulations ?any hints will be great help.thanks in advance.
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Issue on plotting Phase Noise curve
Hi all,I am using Virtuoso Custom IC design Environment version ICADVM20.1-64b.500.21.I ran PSS and PNOISE to characterize ring oscillator's phase noise. PSS and PNOISE setup is shown below.Simulation...
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VerilogA module instance parameter override weird behavior
Hi,I am using Cadence ICADVM20.1-64b.200.21 with SPECTRE20.1.231.isr6 64bitI am trying to build a VerilogA model for a (lookup_table) with instance name "I_ACCUM_CLK_GEN_LUT" that is addressed by a...
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