Pin size on CMOS circuit layout design

Hello,

I would like to ask you about the criteria of making the size of the pins in the layout design, mainly asking about the supply rails (VDD, GND).

I see from the IPs provided by the company they are covering the metal of the complete rail with the pins.

In my circuit I made the VDD pin just like small rectangular taking part from the VDD connection, I found during the post-layout simulation that the Cadence extraction tool start to consider the IR drop just after the pin, which means that if I covered the complete rail with the VDD pin then I will not have an IR drop. For me it looks like I am tricking the simulation or the reality.

I am using Cadence tools version IC6.1.8-64b.500.6 and assura

Thank you in advance

Best Regards