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Physical verification system menu is not working properly
HI All,Recently physical verification system tool is installed and integrated to virtuoso but the menu options are not working. when i am trying to use any option i am getting the following error...
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Convergence difficulties in Verilog A while using equivalent differential...
HiI was using a laplace_nd function to realize a CTLE block as followsV(vp) <+ laplace_nd((0.5*(V(INP)- V(INN)))*rl*gmn , hn , hd);V(vn) <+ laplace_nd((0.5*(V(INN)- V(INP)))*rl*gmn , hn ,...
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$system() command in Verilog-A
Hi,Is there any possibility that I can run $system() command in Verilog-A model. I want to an external script that computes some values and return it to my verilog-a parameter.example:S= $system("sh...
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CDS_thru, LVS, new layer
I am using cadence ic616 and calibre for lvs/DRC/xRC. I added a new layer in the kit (IBM 65nm 10LPe). I want that layer to be shorted during LVS. I learnt that CDS_thru can help with that and I have...
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Running multiple using ADE L, ADE XL, (not at the same time)
Dear all,I've been using ADE to run simulation for a long time. However, I found that when I have multiple ADE instances opened to run multiple simulations, for example, do some basic DC analysis on a...
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ADE simulation setup toolbar missing buttons
Hello:I am using Virtuoso Custom IC Design Environment Version IC6.1.7-64b.500.12ADE L or XL ADE simulation setup toolbar is missing buttons. Mine just looks as follows:How could I restore them to the...
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PDK menu not showing in CIW
Hello:After updating to IC6.1.7-64b.500.12. I am having an issue where the PDK menu is not showing up in the command Interpreter Window. I didn’t have any problem with the previous version of...
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Matlab Simulink Coupler issue
Hello all,I am having a problem where the number of ports on my SimCoupler module will not update within a Simulink schematic in matlab (.slx file). When I double click the module, change the number of...
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Schematic export
Hi,I want to export my digital design schematic in one process to another process in Cadence Virtuoso.I export the schematic in verilog or EDIF.When ı try to export and import the design in EDIF format...
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installation issue in Installscape through DVD
I have started installscape.04.23 in CentOS -7 and when trying to install Cadence tools through DVD got from Cadence, it saysLocation:/run/media/usr1/1908_11042016/IC616_PART-1Does not seem to be a...
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Thermal Noise of Resistor
Hello,I am designing an instrumentation amplifier using the current balancing amplifier architecture. The differential voltage at the input is copied to the sources of the input pair and generates a...
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Stop view
Hello,I am confused about the concept of the stop view. Let's say I have a a two terminal device "X" that I implemented in verilogA and have some parameter in it. Once I save it as a symbol, those...
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How to plot transistor's parameters evolution over time with transient...
Hello,I am sorry if I wrote at the wrong place. (first time)As a beginner on Cadence (student), I would like to know how to plot transistors parameters (Betaeff, Gm, Cgs, Cdg ...) over a transient...
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PEX Compilation Error
Hi,I am using Calibre PEX simulation for post layout simulation. Unfortunately when I load the rules and then trying to setup the inputs, the Calibre gives me the following compilation error....
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HB analysis results with different SELECT options
hii am simulating a balun with its input/output matching network through HB analysis (using SNP file). While simulating I am getting two different values let’s say V1 and V2. Through SELECT options ("...
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Environment variable to prevent "stream in translation complete" pop up...
Hi,Hopefully this is the right forum to post this...I'm wondering is there an environment variable I can set to prevent the "stream in translation complete" message that shows upon streamout and...
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ADEXL: Making Dependent Tests
I've been looking over manuals and posts and can't seem to find an answer to this. Can you make one test dependent on an expression generated from another test.For Example:Test1 : Find a DC Operating...
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ADE L error
I'm trying to design a buffer using tsmc technology file. When I run ADE L , it shows the error below:*WARNING* feature Analog_Design_Environment_L: ERROR (LMF-02018): License call failed for feature...
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Is there any way to use assura compatible file (*.drc , *.lvs ) file in PVS...
My Cadence have PVS plugin and my technology library (tsmc) contains assura_tech file. Is there any way to convert those file in PVS compatible format or any other way to use those in PVS plugin ?thank...
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QPSK modulated signal
hiwhile working on qpsk demodulator i need a qpsk modulated input signal, for which i searched the cadence help and found one telecommunication component with name "QPSK modulator". but i am unable to...
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