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Well proximity parameters (scc,scb,scc) used in PLS simulation
HI,Can anyone tell me how the well proximity parameters are used in model file (.scs) while running PLS simulation?My requirement is to find out how (WPE) well proximity parameters (scc,scb,scc)...
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Spectre: How to get rid of spectre.ic and spectre.fc?
Hi! I am running batch simulations over a large extracted design, so I need to trim down the size of the results directories to the bare minimum. The spectre.ic and spectre.fc occupy almost 50MB each,...
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transistor voltages (65nm / 28nm)
hi the transistor model in 65n has voltages range near 1.2 v (single transistor). What are the voltages in 28nm. (it also has super low voltage transistor). i am new in ic design so apologize for any...
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Making a Summary Measurement in ADEXL
In the ADEXL Outputs Setup, is there a way to add a compound measurement that gets data over all corners run.In my case, I want all edges of a certain measurement to switch within a certain time...
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Is there any way to convert .tf file into .tch file?
I need *.tch file for creating RC corner in tsmc180 technology file. But they provide me with .tf file ? Is there any way to convert it ? If not, what format of file I should search for which could be...
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RMS and AVERAGE Calculation with respect to power.
I have designed a custom 5 bit counter. The "Pulse" Inputs are applied to the counter so that all possible input combination are applied to the counter (from 00000 to 11111). The output of counter is...
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How to differentiate trace name using "Plot signals from all the open DBs" in...
Hi,I'm using ViVA XL 6.1.7. When I use "Plot signals from all the open DBs" feature for comparing signal, it doesn't show the trace result dir at trance name.So, it is difficult to differentiate the...
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Title Block Properties Moving
Hello,I've created custom title blocks with custom properties. I have selected the justification, font, size, etc. for where they are located on the title block, and have placed them appropriately....
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Usage of variables belonged to different measurement functions in spectremdl
Hi,I am using spectremdl for measuring the performance of my analog circuits. During simulation, one variable is generated using the DC run and the other using transient run. I need to calculate a...
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.lib files generation for custom analog design
Hello,I wish to generate .lib files from a cadence library analog cell, Is there a direct way to generate that from ADE GXL testbench ? I read in this forum about DCM but couldn't find it in GXL ?...
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.cdsplotinit and trying to print schematics on 11x17 paper
Hi,We recently installed new printers which have the option of printing to standard Letter size (Drawer 1) or 11x17 (drawer 2). I added the printer to my .cdsplotinit file however, every time I select...
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vbit source in analogLib
I tried using the vbit source from analogLib in cadence virtuoso 5.1.0 04/26/2009. I would like to simulate my design with a specific bit pattern. but it gives me error. please see attached snapshot...
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Basics about wire labels and general text
hi 1) Can a wire be defined with two wire names with some dummy element between them. (actually during my simulation tests i have to bypass the switch to check the o/p therefore one name either at...
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How to reduce time needed before transient simulation to be started in case...
Hi,I have to run transient simulation for a very large circuit. But every time, before starting transient simulation( simulation for different times), it is taking a significant amount of time to find...
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Using AMS pads on Virtuoso Layout L
Hi,I am trying to include AMS pads (process AMS C35B3C3) in my layout but I am getting the BAD_SUBSTR_SUBTAP_FLOAT_ERC error when running Assura DRC. Regarding the pins, I am using the PIN PAD layer...
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Problem of RC Extraction with GPDK45nm(gpdk045_V_3_5)
HiWhen I was running RCX extraction using ASSURA with gpdk045 model. Always I'm getting warnings and then failed to extract layout. From the log file, some libraries models are missing in gpdk45.Please...
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APS simulation: When a DC supply isn't DC
I'm getting strange behavior from an APS run and I'm hoping I can get some suggestions to debug/resolve the issue. Basically, my waveforms are skipping around. The problems started when I added a...
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scs file calls a verilogA
Hello, I have a ".scs" file that calls a verilogA model. the line in the .scs file that does this reads the following:memr_TMO_test p n memr_TMO_test HRS=HRS1 LRS=LRS1 Vtp=VtP Vtn=VtNthe verilogA model...
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Align Figure groups together
I'm trying to organise my schematic into various groups based on their function.I can align the instances in each group but can't align different groups together, is this possible using the align...
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Syntax for device check violation file assert statement
Hello,I would like to ask how to write device check violation files (for example devcheck.scs) I can include in my model files and use to check for violations.I believe the correct syntax for example...
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