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Changing swept variables plotted

March 27, 2020, 4:02 am
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I'm not entirely how to ask this question without sounding weird so here goes nothing (sorry!)

I have a simulation in ADE-XL that sweeps two variables; let's call them A and B.  I want to plot A as a function of time grouped in such a way that it's every variable of B (with the lines being A values at a fixed B and each line is a different color; color representing the different B values) but when I select all of the data points (each run produces 1 data point) and I select to plot them in the GUI, it plots B values swept for each constant A.  Is there a way within the GUI or some other way to swap these as a function of each other?

I suspect the way that it's defaulting this graphing is that if you order the runs by their run number, B is swept before A is swept (if it was a nested for loop, B would be within A).

I hope this made sense.  Realistically this is a small enough data set I can just export it and plot it with something else but there are more analysis I'd like to do after that frankly is just easier with the ADE calculator not to mention I really should learn how to use this tool.

Ideally I'd like to learn how to group these sweeps and extract only this data then run a monte carlo but that's for another day.

Thanks!

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Variable Pnoise Stop Frequency

March 31, 2020, 3:43 am
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IC 6.1.8.090

ADE Explorer

I am running a shooting PSS analysis to determine the output frequency of an oscillator. I also run a PNOISE analysis to report a Jitter measurement based on this PSS.

However, the oscillator output frequency varies over PVT. I would like my PNOISE simulation to have a stop frequency of half the oscillation frequency over corners.

Is this possible (or even reasonable...)? (Taking the calculated oscillator frequency and passing that value to the PNOISE analysis setup.)

Many thanks,

Conor

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Different waveform loading with each corner in ADE Assembler

March 31, 2020, 4:33 am
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Hi,

I am trying to load the some frequency-gain tables simulated by an external tool into the Outputs of ADE Assembler.

To change the table with each Corner, I merged several tables into one file and tried to read the data by selecting the data corresponding to the Corner with xCol and yCol of getAsciiWave as follows.

  • getAsciiWave("./table.txt" 1 VAR("sel") ?xskip 0 ?yskip 0 ?formatFload nil ?xName "freq" ?xUnits "Hz" ?yName "amplitude" ?yUnits "mag")

However, when I set the above variable "sel" into yCol in getAsciiWave, the file could not be read with an error. Of course, when I directly set 2 or 3 or something integer as yCol, these are successfully selected and loaded.

Is there any mistake? or is there another way to select and load tables by variable?

Regards,

Kaputt.

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imporing TI spice mode(.lib) to virtuoso

March 31, 2020, 4:43 am
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I want to import some Ti opamp models to virtuoso.  (.lib &pspice model)  .

Anybody know how to do that?  If you know, could you tell me the detailed method? 

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Is it possible to get ADEXL simulation parameters and all other related input stimulus

April 1, 2020, 2:04 am
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I have an ADEXL maestro view which I can run simulations by opening the view and pressing the green button, however, I want to run the simulations using spectre from command line.

To do this I need a way to extract all the simulation information (netlist, input stimuli etc) to a file so I can run the simulation from the command line using spectre and the extracted file.

I will appreciate any assistance with this.

I am using IC6.1.7-64b.500.20

Thanks

Genas

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Some GUI windows fail to launch in Virtuoso

April 1, 2020, 7:42 am
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Using IC6.1.7 (sub-version  IC6.1.7-64b.500.23) there are instances when a popup window will fail to be drawn on the screen. This happens often when trying to edit graph properties in VIVA or editing parameters in ADEXL. Looking at the CIW log with no filtering, it looks like the command is issued, but no window appears.

One possible cause that I can think of is I am using Virtuoso remotely. I never experienced this issue using SSH+X11. However now I don't have access to my university's LAN, I am using x2go (an open-source version of NX). Is this a known bug with Cadence Virtuoso and x2go/NX? Or is something else happening?

For reference, I am using Virtuoso on a CentOS 7.7.1908 server which I access using x2go 4.1.2.2 (an open-source version of the NX remote desktop tool).

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Flicker noise in switched-bias pMOS

April 1, 2020, 3:29 pm
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Hello,

This is my first post in the forum so I do apologize if my question doesn't respect the community guidelines.

In 1990, a research team proved that cycling a FET transistor from inversion to accumulation has the effect of reducing its intrinsic 1/f noise. It is not merely a reduction due to a change in signal gain caused by the transistor being cut-off half the time, but instead caused by a "refresh" of the "long time memory" of the energy states at the Si/SiO2 interface that is believed to cause most of the flicker noise.

Many other papers followed that again proved this concept.

I was wondering if in Virtuoso this phenomenon is modelled.

I am using periodic steady-state analyses and periodic noise (PSS and PNoise) on a common source switched-bias pMOS but I cannot observe this effect no matter what the cut-off gate-source voltage is set to.

Cadence Virtuoso is version 6.1.8.

Thanks,

Giuseppe

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What is the LEF / LDE / LLE?

April 1, 2020, 9:48 pm
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Hello. I am Layout Engineer.

And now doing study for DRC, LVS, DFMC and etc.

But now new 3 jobs LEF / LDE / LLE..

1. What is the LEF?

I think that is Library Exchange Format. For GDS / OAS format to ASCII format.

But some people LEF is Layout abstract for top-level connectivity..

What is different?

2.What is LDE?

Use LDE_CHECK. (CDM_CHECK, GDS_CHECK, etc)

What is fuul spelling LDE?

3.What is LLE?

I think that is Local Layout Effect. and result is STI and WPE option.

Thanks for reading. My English is bad.. sry.. but if you help me I really happy today! XD

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How do I sweep a simulator option parameter (gmin, vabstol, rforce,...) in ADE Explorer / XL?

April 2, 2020, 2:26 pm
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HI all,

I'm trying to optimize the circuit convergence and I would like to sweep parameters  like gmin or rforce, which are defined in the simulator option card.

How I could do it? Any suggestion?

Thanks in advance

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How do I load parametric analysis results in ADE L again to plot

April 2, 2020, 4:31 pm
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Hello,

I am doing a simple parametric analysis from ADE L and sweeping on 4 values: L (20 points), Vd (10 points), Vb (10 points), and Vg (50 steps); this gives 100,000 simulations. I am interested in DC simulation only to gather information on (id, gm, gmb, vth, various junction capacitance, ... etc). I am expecting to get various plots of the mentioned parameters on the y-axis and Vg on the x-axis (since Vg is set as the last variable in parametric analysis). My settings are shown below:

My problem is: Cadence finished the 100k simulations in about a week for the schematics below and kept hanging on the last run for 3 days (I assume it was trying to finalize or save the results or something..), but then it crashed & I didn't get to see the results.

My questions:

1) Now I have 100k directories in the simulation directory with each run in a separate folder, but I don't know how to load them back in ADE and get the same plots if the simulation finished normally. I know how to load a single run in the results browser only by loading the psf directory, but I don't know how to do it in the parametric analysis multiple run. Is there an easy way to restore the results without running the simulations again? My final goal is to get plots similar to the image below (Not an exact result image but similar)

2) Normally after simulation finish, I plot the curves then select each bundle and export it to a .matlab file. Is there a way to do this automatically after simulation finishes? It takes a long time to group all curves as shown above and save it in a file separately; then repeat this for every device in my schematics. 

3) I noticed that parametric analysis is very fast at the beginning of simulations; each DC simulation takes less than a second. Then after a day or two in simulating, a single run takes 10 seconds, and towards the end it takes up to 20-30 seconds to do a single run. I tried APS (High performance simulation), but it is even slower with the first runs, so I expect it will be worse towards then end. Is there any other way to run this kind of simulation in parallel or more efficiently?

I am using the following Cadence versions:

MMSIM Version: 13.1.1.660.isr18

Virtuoso Version: IC6.1.8-64b.500.1

irun Version: 14.10-s039

Spectre Version: 18.1.0.421.isr9

Many thanks in advance!

Kindest Regards,

Nader Sh.

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Unwrap a waveform

April 5, 2020, 7:02 pm
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Hi All

In Viva, is there a function available to unwrap a waveform by defining its wrap-over value. For eg: please see the below plot. There are phaseDegunwrap and phaseRadunwrap, they don't serve this purpose. 

I would be grateful if I can get few pointers towards solving this.

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Worst case delay measurement

April 6, 2020, 9:13 pm
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Hi,

I have simulated an inverter in 180nm. I'm told to calculate the propagation delay and worst case delay of the circuit.

What is the method to calculate worst case delay either using calculator or graphical output ?

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How to access Metal enclosures over Via

April 8, 2020, 2:52 am
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Hi All,

I am trying to access Metal Enclosures over Via using the via~>viaHeader~>overrideParams

however, for some via I do get the layer1Enc and layer2Enc and for some I don't get the Via Enclosure.

I get these below outputs


a=geGetSelSet()
a~>viaHeader~>overrideParams
((("cutRows" 4)
("cutColumns" 1)
)
)
However the Metal Enclosures are as follows

            Metal1 Metal2

Left       0.5       0.8

Right     0.5       0.8

Top        0.5       0.8

Bottom   0.5       0.8

Please tell me if I doing something wrong in this.

Thanks in Advance

Utkarsh

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Export Netlist with VerilogA subblock when there is no ADE license

April 8, 2020, 9:33 pm
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Dear all,

I would like to ask how to export netlist with VerilogA subblock when there is no ADE license.

I can export normal schematic view by using si -batch -command netlist command with a defined si.env file.

However, when exporting a schematic with VerilogA inside, the following error is outputed.

Virtuoso Framework License (111) was checked out successfully. Total checkout time was 2.40s.
*Error* dbClose: argument #1 should be a database object (type template = "d") - nil

Here is my si.env file

simLibName = "xxx"
simCellName = "xxx"
simViewName = "schematic"
simSimulator = "auCdl"
simNotIncremental = 't
simReNetlistAll = nil
simViewList = '("auCdl" "schematic")
simStopList = '("auCdl")
hnlNetlistFileName = "netlist"
resistorModel = ""
shortRES = 2000.0
preserveRES = 't
checkRESVAL = 't
checkRESSIZE = 'nil
preserveCAP = 't
checkCAPVAL = 't
checkCAPAREA = 'nil
preserveDIO = 't
checkDIOAREA = 't
checkDIOPERI = 't
checkCAPPERI = 'nil
simPrintInhConnAttributes = 'nil
checkScale = "meter"
checkLDD = 'nil
pinMAP = 'nil
preserveBangInNetlist = 'nil
shrinkFACTOR = 0.0
globalPowerSig = ""
globalGndSig = ""
displayPININFO = 't
preserveALL = 't
setEQUIV = ""
incFILE = ""
auCdlDefNetlistProc = "ansCdlSubcktCall"

Could anyone help me this problem? Thank you.

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Spectre S-parameter analysis

April 10, 2020, 3:00 pm
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I am doing s-parameter analysis using spectre "SP" analysis.  Few question : 

1) I have placed 40 ports ( port from analogLib) and attached to the appropriate nodes in the circuit. I have numbered them as 1 to 40.  Do I need to tell the tool which ones is input and which ones are output ?

2) In the ADE analysis GUI I have given the port name in the following form. 

3) Is there any way to put all the S11/S12/S13......etc in the output so that I can view them in the result analysis as soon as the simulation is done ? 

4) How do I save the s-parameter result in a touchstone file format ? 

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VIVA Plots across many Points

April 14, 2020, 12:54 am
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Hello Cadence,

I am trying to plot the 3db point while varying the number of fingers and the finger width of two MOSFETs, I really only have the two variable though since the second mosfet matches the first one.

For some reason when I plot this after running adexl I only get points, It doesn't connect the dots, my guess is maybe there are too many variables; I haven't had this problem before. I guess my general question is how can I prevent this from happening? Also, how can I fix this in VIVA if I am to run into this problem again?

Thanks!
Charles

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plotting waveVsWave across corner+global variable sweep in ADEXL

April 14, 2020, 9:40 pm
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Hello,

I'm running a simulation across corners, while stepping through a Global Variable in ADEXL. In this case the variable is TRIM_CODE, and I want to evaluate the trim gain, i.e., dVOUT/dTRIM_CODE.

If I run only one corner, I can do something like this:

waveVsWave(?x VAR("TRIM_CODE") ?y v("/VOUT" ?result "tran")

and then do "deriv" on that, which seems to work.

But when I decide I want to add couple corners, I can no longer do what I did above. With corners enabled, it appears that waveVsWave function "flattens" out the data and groups all point under one curve (for which 'deriv' returns nothing).  And I can't figure out how to do waveVsWave(?x VAR("TRIM_CODE") ?y v("/VOUT" ?result "tran") per corner, as a workaround.

Is there perhaps a better way getting what I'm after?

(I'm on version 6.1.8)

Many thanks in advance for your help,
David

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Some DRC errors regarding SP and DP

April 15, 2020, 8:01 am
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Hi, I am new using CADENCE, I want to create a layout with DP inside a p Silicon substrate were all my IC will behold. After I run the DRC with Assura I got the following error:

-> (SP, DP) only allowed inside ((RXHV RXHV_IBM) sized by +0.2) sized by -0.2)or in RXHV_IBM touching (text on level RXHV_IBM {NFET12MH_REV_1.0}

I try to fix this creating an RXHV over DP, but then I got this new error which I don't know how o fix:

-> RXHV with 0 or more than 1 RXHV label cadence 

Can anyone help me with this problem? Thanks

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Conversion of old Simulation Files

April 15, 2020, 9:46 am
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Hello,

I have some old libraries which contain schematics (in the .cdb format) and ADL states (which saved in the directory path instead of Cellview path). 
I copied the specter folder of each library to its Cellview path, and then I used the conversion toolbox of Virtuoso to convert them. Still, only the schematic converted to .oa file and are visible in my new libraries.

How can I convert the ADL states as well? Regarding the ADL states have been saved in the directory path, should I copy them one by one to Cellview directory (however it didn't work), or is there another way to recall them? 

Best,

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plotting Smith charts

April 15, 2020, 11:10 pm
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Hello,

I'm running an .sp analysis with a simple setup--port set to 100ohm, with 100ohm load.  I'm plotting results on a Z-Smith, which i thought should give me Re(Z)=1 (normalized)... but instead I'm getting something like 2e-12 as the prime center.  I don't understand why this is the case.  I'm relatively new to Smith charts, but I'm guessing the plot actually shows reflection coefficient, not the impedance?  If this is the case, how can I request an impedance plot?

I'm on version 6.1.8.

Many thanks in advance for your help,
David

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