I want to ask about simulation procedure of a digital LDO , how in a feedback it can be simulated? What are the initial condition that need to be given for successful simulation while iterating in feedback. Kindly suggest possible solution.
↧
LDO design and simulation
↧
How do make the clock 25% duty cycle with jitter capability
How do make the clock 25% duty cycle. I am looking for creating 25% duty cycle ( or a certain High pulse width ) clock where I can add random and deterministic jitter.
Hi Andrew,
My apology for not starting a new thread and just replying to an really old thread with the above question. Here I am starting a new thread on this.
Your Answer on this :
In this case I'd suggest you use a "bit" source (the Source Type being bit):
It's not quite working. Here's what I have used :
Since the fall edge sloe is not modified, you get a distorted waveform. How do we fix it ?
↧
↧
Using DFT to analyze a time-interleaving track and hold circuit
Hi,
I am evaluating the frequency response and linearity of a time-interleaving track and hold circuit.
The input signal frequency can be up to 28GHz, and the sampling frequency (Fs) is 7GHz.
In my test bench, I set the sample number (Ns) as 64, and the input frequency is set with the formula Fin = (Ni/Ns)xFs, while Ni is prime number, the strobe period is set as "1/8/Fs". In the DFT setting, the starting point is set as "50/Fs", and the end point is 50/7G+Ns/Fs. In this way, the sampling frequency in DFT is the same as that in real circuit.
My question is:
1. For the input signal, whose frequency is higher than Fs/2, its fundamental tone would be folded back to 0~Fs/2 due to aliasing. Can I still use DFT to capture the fundamental tone and its harmonics magnitude correctly? Is it possible that the harmonics overlap with each other? If so, how should I set the input frequency to avoid this problem?
2. Can "Spectrum Measurement Tool" in ADE can capture the correct fundamental tone while signal frequency is higher than sampling frequency?
Thanks and regards,
Yuto
↧
Dynamic temperature variation of a SPECIFIC component during transient simulation
I know how to do dynamic temperature variation during transient simulation and plot temperature as well as any parameters vs time.
But what if I want to keep temperature of ALL components to some fixed value during transient simulation but dynamically vary the temperature of only *one specific* component, for example some BJT device?
Is such thing even doable in cadence ADEXL?
↧
Pass veriloga parameter to parameters in ADE XL
I'm working on a circuit which requires long transient simulations for a part of the circuit to settle, and I am therefore trying to utilize the State File options of spectre.
I save the state at a point in my simulation when the load has settled, and start simulations from that point.
I know I cannot change the circuit and use my state file, but I can change the parameters of devices, which is what I want to do.
This works fine in ADE L along with parametric sweep.
But, when I try to sweep global variables in ADE XL, the variables does not change in the simulation. If I change parameters the devices do change in simulation.
My problem is that I have a veriloga block, and it does not seem to be possible to pass a parameter from the veriloga block to the parameters in ADE XL.
I can define the parameter of the veriloga block to be equal to the value of a global variable, but since the global variable has no effect when using a state file, that approach is not usable.
I have not been able to figure it out from the documentation how to pass the veriloga parameter to ADE XL parameters.
Does anyone know how to do this?
Or how to make variables in ADE XL work when using a state file?
Regards
Jakob Toft
↧
↧
Pnoise vs Transient noise
Hello!
I am simulating the noise effect on an opamp output. The output is buffered so I used both pnoise and transient noise to calculate the rising jitter rms of the output signal. My problem is that the pnoise and transient noise give me pretty different results. (pnoise: 2.8ps; trans. noise: 4ps, these values make big difference to my design) Please can you tell me which result should I rely on in such case. My simulation setup, simulation results, and circuit test bench are attached as below. Thank you a lot!
↧
How to measure the performance of a PLL ?
Hi,
I recently built up a CMOS PLL circuit . And so far, in the trans simulation, it would be stable (locked to reference frequency) after a few uS.
My questions are :
1. What kind of simulations would be applied to measure the performance of PLL in general? Because we can only run the trans simulation right now.
2. I tried to run pss, however, as we have another signal source as reference signal, pss simulation would not tolerate that. Is PSS possible and necessary?
3. I tried to run HB simulation, the data it generated is soooooo much which filled our disk and errors showed up. So I guess that is impossible for me .
4.I saw many papers ploting the closed loop gain and phase margin. But I don't know what simulation gives that result ? What should I do if I want to see the closed loop gain and phase margin ? What's the meaning of that two figues?
5.The simulation for the whole circuit usually takes few hours with aps++ . Will it be faster if I use spectre X ? It is said it would be faster 3-10 times in the Ad.
If anyone has any suggestion or experience and would like to share with me, I would be grateful.
Thank you !
↧
Verilog-A Simulation
Hey All,
I have just started using verilog-a, and i am trying to simulate the V-I characteristics for a resistor, on DC sweep i neither get any output nor any error message, could anyone help me out with the same.
I have attached images of the output log and the verilog-a code for the same
Thank you 
↧
Improving Virtuoso Speed
Hi,
I'm unsure if this is a concern for the Support, but the setup we use with virtuoso (ICADVM18) is pretty slow. I need to wait a few seconds for every window to open, a time during which I can see small dialog windows popping up for a few milliseconds. Even more, this affects nearly every task: Scrolling in layout, starting simulations, opening simulation results etc. takes for ever.
I'm not sure what exactly is going on, I guess the PDK we're using is adding some stuff which needs some computation time, but the difference is tremendous (compared to a simpler PDK we use for our students).
Besides support, is there anything I can look for myself? Can I turn off some submodules I don't need? I'm not sure if this is a valid complain, but even a simple DC simulation without any loading of model files, only analogLib components takes 10 to 20 seconds, of which the actual simulation time is below one second.
Sorry, I'm aware that this is very broad and difficult to debug from remote, but perhaps there are some tips on how to improve general performance.
Kind regards,
Patrick
↧
↧
Can I analyze LDE effects on finfet design using GPDK cds_ff_mpt_v_0.5
hello. I want to measure the effects of layout dependent effects of analog circuit design (opamps) using finfet technology. I do have access to cds_ff_mpt_v_0.5 GPDK but in the description of this GPDK nothing is mentioned about LDE effects. is there any way that I can use LDE analyzer in virtuoso for this PDK? Will I be able to see these affects in my simulations?
Thanks,
Mehrnaz
↧
CDF Parameters: No master specified for instance when running simulation
I've created a simple NOR gate. I want to be able to adjust the width and scaling factor of the NMOS and PMOS transistors in the circuit. Therefore, I have gone ahead and given them the following pPar parameters:
- pPar("p_m") for the scale factor of the PMOS
- pPar("p_w") for the width of the PMOS
- pPar("n_m") for the scale factor of the NMOS
- pPar("n_w") for the width of the NMOS
An example of how I set it up is shown here:
I then gave these parameters some default values via the Tools -> CDF menu. They look like the following:
All is well. I setup a circuit and then a simulation
However, when I attempt to run this simulation, I am bombarded with a list of errors:
Also, I see new design variables are added to my analog environment window:
I am not sure why I am encountering these issues. I setup the environment variables using pPar so that they can be set from a parent. I also had supplied defaults. How can I resolve this issue?
↧
Difference in gm and Id values obtained in hand calculation and simulation results ?
Hi,
I simulated a nmos in 180nm technology and found its parameters. The hand calculated values for gm and Id were not same as simulated values (different Vgs values were used).
Specs: Vdd = 1.8V; W=420nm; L=180nm; Vds=0.9V.
↧
assign a sub list to the range of nested foreach loop
I would like to use Ocean to group a few corner cases to a single plot after ADE XL corner sim. For example, I have these corner numbers (for fetching tran analysis results), and I could group them like these, at temperature = 0 degC, plot VT("/out") from data directory list(1 2 3), and at temperature = 65degC, plot VT("/out") from data directory list(4 5 6), the Ocean script would be something like this:
foreach((temp corners) list(0 65) list(list(1 2 3) list(4 5 6))
newWindow()
foreach(corner car(corners)
openResults(corner)
plot( VT("/out") )
)
So that for each temperature, there is a window of plot of three curves of VT("/out"). But the above syntax is obviously not quite right. Any suggests, please?
↧
↧
Ascending to top level when a simulation is run
I’ve noticed that when I run a simulation using ADE Explorer, it automatically ascends to the top level of the simulation testbed. This is not always desired. For example, if you are looking at DC voltages and device operating points in a sub-circuit, ascending automatically to the top level means that you now have to descend back to the sub-circuit every time you run the simulation. Is there a way to disable this behavior of automatically ascending to the top level when the simulation is run?
↧
pnoise jitter Jee plot button disappeared
Hi everyone,
With ADEXL, in a shooting pss + pnoise jitter analysis, I try to plot the jitter (edge) Jee vs. df, but the "plot" button has disappeared! I can only get the integrated noise value; I was still able to do that a couple of weeks ago...
What could have happened ? How could I plot it ??
I use the IC6.1.8-64b.500.5 version of Virtuoso.
Thanks in advance for your help.
↧
Eldo netlist generation with ADE L.
Hello,
I try to generate an Eldo netlist from ADE L. I configure the simulator to EldoD, but i got this error:
ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'eldoD schematic verilogAe AFE_Gas_Sensor', for the
instance 'M0' in cell 'simple_test'. Add one of these views to the cell 'P_LV_18_MM' in the
library 'UMC_18_CMOS', or modify the view list so that it contains an existing view.
I saw another post talking about the same topic, but I am not able to correct my problem.
I guess writing the good parameters in Switch View List and Stop View List could help. But I do not catch how to know the right parameters to write into these boxes ? Is it technology depend ?
Hope you could help me.
Have a nice day,
Sylvain.
↧
How to install PVS
Hello, please tell me if I can install PVS separately for Cadence. What commands do I need to use for this?
↧
↧
Spectre: possible to use netlists for subcircuits in ONLY selected blocks?
Hi! Is it possible to instruct Spectre to use netlists for subcircuits in only some blocks of a hierarchy, and other views (e.g. schematic) elsewhere?
Our foundry supplies netlists with extracted RC parasitics ("LPE netlists") for the standard cells, and I can make Spectre use those (instead of the schematic views) if I specify so in the Hierarchy Editor (config view). However, this can only be done for *all* the instances of a given cell, irrespective of location in the hierarchy, which results in unnecessarily long simulations as the LPE netlists are then also used for the standard cells in non-timing-critical blocks. Instead, I'd like to enforce the LPE netlists for just the cells in timing-critical blocks. Is this somehow possible?
Note that even though the "tree-view" mode in the Hierarchy Editor would seem to enable such enforcement, when simulating the resulting config view Spectre aborts because of finding multiple definitions for the standard cells ("[...] a subcircuit with the same name has been defined [...]" error).
I even tried making a copy of the standard cell library where I deleted all the schematic views, and use this lib (+the LPE netlists) for the cells in the timing critical blocks, but Spectre still cannot resolve the difference as the subcircuit names are the same for the cells in this and the original library (I guess I could rename the cells too, but this would then involve a lot of work for replacing all the instances in the all timing-critical blocks, so I disregarded it as a solution for not being practical).
(In desperation, I also tried to somehow use the MTS option in Assembler to this purpose, but it clearly seems not intended for such usage... or is it so?).
Thanks in advance for any help!
Regars, Jorge.
↧
Segmentation fault in a PSS simulation (ADE-XL)
Hi Andrew/someone,
I have a testbench in ADEXL (a PSS simulation) that returns a segmentation fault.
I am said to "submit the case via Cadence Online Support", could you please explain to me exactly the procedure to follow?
Can I submit my netlist only? is the tar file necessary? if so in which path do I run the "mmsimpack" command and which command exactly may I run?
etc, etc...
Sorry again for my "noobitude" in Cadence CAD/Unix :-)
Thanks and best regards
↧
How to add a new component-part in Virtuoso
Hi ,
I have this spice code from ALADIN website, it is supposed to be the spice file for two nmos transistors connected in a certain way in one chip as in the attached figure.
I want to create this new component in Virtuoso to uses in the schematic.
I searched a lot around and I found CDF editing tutorial but it does not work since the parameters does not show up in the CDF form. Could any one help me in this.
Thank you
*-----------------------------------------------------------------------------------------* d g s b v+
.subckt 114813 1 2 3 4 5 params: vtn=-1.3811
m1 1 2 3 4 ncg l=7.8e-6 w=138e-6 as=0.603e-8 ps=0.478e-3 ad=0.161e-8
+ nrd=0.3 nrs=1 nrg=25 nrb=35
.param vtx={vtn} cox=1.0 ires=0.41 pox=1.0 M=1
.model ncg nmos (level=2
+ gamma=0.035 lot/4/uniform=-.22 dev/uniform=.04
+ vto={vtn} lot/2/uniform=.2 dev/uniform=19e-3
+ Uo=650 lot/3/uniform=40 dev/uniform=5
+ Ucrit=0.7e4 Uexp=.1 Vmax=1.6e5
+ phi=0.65 tpg=+1
+ nsub={1e16*ires} neff={10*ires} nss=0.7e11 nfs=4.4e11
+ tox=(0.055u*cox) lot/8/uniform=9.1% dev/uniform=.05%
+ Cgso={.94n*cox} Cgdo={.59n*cox} Cgbo={.138n*pox} Xqc=.42
+ cj=.39m cjsw=264p xj=1.0u
+ ld=0.8u lot/uniform=.19 dev/uniform=.02
+ wd=1.05u lot/uniform=.42 dev/uniform=.1
+ pb=.9 js=20e-6 mj=.5 mjsw=0.18
+ kf=.75e-28 rsh=10 lot/1/uniform=4 dev/uniform=.5)
dbv 4 5 dps 0.8e-8
dbd 4 1 dps 0.8e-8
dbs 4 3 dps 0.8e-8
dbg 4 2 dps 0.8e-8
dgv 2 5 dps 0.8e-8
.ends
↧