Quantcast
Channel: Cadence Custom IC Design Forum
Viewing all 4911 articles
Browse latest View live

hbnoise noise figure

$
0
0

Hi,

I got some weird result when using hbnoise simulation. I am simulating a down-conversion mixer. I followed the cadence tutorial setting.

My simulation condition is hb:Flo =2.4GHz harmonic=50, hbnoise Fbb = 1M~10MHz, maximum sideband =1 (not the cause of quesiton)

My question is that Direct-plot generated "noise figure" is much high than the calcuated "noise summary" result.

I attached the result is the below figures, the noise figure from Direct-plot is ~9dB, but the noise summary is much lower than 9dB(/RF is port,/I0 is mixer).

I am wondering the way hbnoise calculate noise figure is different from noise summary?


How set "control buttons" enabled by default inside Palette

$
0
0

Hi,

is there a way to set visible the "control buttons" as default at each Virtuoso session? I search for some varibale to set but I didibn't find anything

Regards

Mauro

SPICE cellview: how to use?

$
0
0

Hello everyone,

I've just noticed that there is a "spice" cellview from the dropdown list in the create new cellview form. By creating a spice cellview the text editor will open. Where can I find information about the intended use of this cellview type? I was not able to use the appropriate search terms in the knowledgebase, i.e. support.cadence.com. Apparently "spice cellview" was not enough.

I imagine a use-case like this: someone adds a spice model file this way. After creating a symbol and probably some termMapping, the netlister and simulator will pick up the "spice" cellview through switch view list or hierarchy editor. With other words: there is no need to add the spice model file with Setup -> Model Files, and add the "model" CDF parameter in the CDF Editor. Maybe a terminal/port check between the spice netlist and the symbol could have been implemented.

I'm using ICADV12.3.

Thanks!
Zoltan

Problem getting OCEAN xl to print correlation from monte carlo run

$
0
0

I had the ocean script as follow,

monteExpr( "a" "calculation..." )
monteExpr( "b" "calculation..." )
monteCorrelate("a b" 0.5)
monteDisplay()

The summary form monte carlo was working, but nothing gives seems to give me the correlation of a and b.

I also tried monteOutputs(), But it only error out at the end.

If someone knows how to print correlation of monte carlo run from ocean xl that will be very helpful, thanks a lot.

current measure statement

$
0
0

Hi

What is wrong with the following statement;-

.meas tran ir0 find i(Ibot.Iarray.Il.I128.Il.I0_7.Itr.N0:s) at=6n

When i use this it keeps saying the following:-

WARNING (MDL-358): ......meas" 6: probe 'I( Ibot.Iarray.Il.I128.Il.I0_7.Itr.XN0.s:1 )' is invalid.

I am using Spectre (R) Circuit Simulator Version 19.1.0.237.isr3 64bit -- 3 Jan 2020

Thanks

WB

Instance terminal mapping within IC5.10.41.500.x.x running on RHEl6.9

$
0
0

Hi 

I found instance terminal mapping is broken within IC5.10.41.500.x.x running on RHEL6.9 so that the calculator function IT("/PATH/Instance/Terminal") won't work. However, if I open a result browser, I can find that all the terminals are labelled with Instance\:1, Instance\:2, etc. They can be accessed and plotted.  

If I switched the OS platform to RHEL5.6, which I still have. The problem disappears. Is there any switch to set in order to make it work? Thanks.

Best regards

Patrick 

path appearing different within IC616 and IC618

$
0
0

Hi,

I just meet an issue while I transferred OA from IC616 and IC618. I have a path, (86.555 125.196) (86.052 125.196) (86.052 125.188) (86.129 125.188) , and width=0.2, endtype truncate. I opened the cell and had a look, the appearing is different between IC616 and IC618, then I streamed out, the 2 gds file are also different on this path. so I guess it is the difference of the tool behavior. Is there any way to transfer OA from IC616 to IC618 with original looking.

Best Regards,

Jay

window focus policy issue (Always focus Navigator first time)

$
0
0

Hi,

I use Cadence version (IC6.1.8-64b.500.9).

When I open Virtuoso schematic or layout, the Navigator is focused first time, so I can't do any infix command before I click or move out cursor and move in again.

Once I click the schematic window or move cursor out and in, the focus policy ( CanvasDelay) is working correctly.

When I use version IC6.1.8-64b.500.6, there is no issue about that. However I change the version later 500.8, it happens.

Do you have any ideas?

Thanks


EvalType in Cadence ADEXL

$
0
0

Hello,

I read the help documentation of ADEXL couldn't understand what the function of EvalType in the Output Setup of ADEXL interface. Basically it give two options: Point and Corners, by default Cadence set it to Point but what either means to choose the proper selection

Thank you

I want a user manual for the switch in analoglib. where I can get this?

$
0
0

I want a user manual for the switch in analoglib. where I can get this?

Negative Power Numbers During the Synthesis Over a Custom Cell Library (Liberate)

$
0
0

Hi,

I have a requirement to characterize a set of standard cells of following type : 

All of these custom cells have the same transistor arrangement, i.e. a transmission gate pair followed by an inverter. Since the inverter isolates the inputs from the loads of the cell, this cell can be characterized over a wider slew/load range. (i.e. "Liberate - Characterization Setup for Special Mux Cells" RAK (i.e. MXIUI2X1)) .

When a design is synthesized over this custom cell library, the default power reported during the synthesis becomes negative :

i.e. 

However the power report based on the switching activity shows positive power numbers. Moreover for the library of standard CMOS type of cells (both inputs and outputs are buffered) using the same liberate settings, this is not observable ! I use following power calculation settings in the .tcl script : 

#----------------------------------------------- Power -----------------------------------------------------------------------------------------------
### Leakage ###
set_var max_leakage_vector [expr 2**10]
set_var leakage_float_internal_supply 0 ;# get worst case leakage for power switch cells when off
set_var reset_negative_leakage_power 1 ;# convert negative leakage current to 0

### Power ###
set_var voltage_map 1 ;# create pg_pin groups, related_power_pin / related_ground_pin
set_var pin_based_power 0 ;# 0=based on VDD only; 1=power based on VDD and VSS (default);
set_var power_combinational_include_output 0 ;# do not include output pins in when conditions for combinational cells

set_var force_default_group 1
set_default_group -criteria {power avg} ;# use average for default power group

#set_var power_subtract_leakage 4 ;# use 4 for cells with exhaustive leakage states.
set_var subtract_hidden_power 2 ;# 1=subtract hidden power for all cells
set_var subtract_hidden_power_use_default 3 ;# 3=subtract hidden power from matched when condition then default group
set_var power_multi_output_binning_mode 1 ;# binning for multi-output cell considered for both timing and power arcs
set_var power_minimize_switching 1
set_var max_hidden_vector [expr 2**10]
#------------------------------------------------------------------------------------------------------------------------------------------------------------------

What could be the reason for the negative power numbers ?

Thanks in advance

Anuradha

Is CDL netlist *.PININFO pin1:O pin2:I pin3:IO property a syntax requirement?

$
0
0

Trying to understand what tools read the direction of pins in the CDL netlist.

Is this syntax a requirement? Which tools will give out errors when reading the CDL without the directions?

Where can i find "Syntax manual" sort of guide for CDL format?

spiceText view with AMS OSS netlister

$
0
0

I have a spice model for a device imported as a spiceText view. It runs with spectre and AMS when using the unified netlister but with the OSS netlister the models don't seem to be included.

I would just use the unified netlister but due to another issue I need to use OSS. Any suggestions how to fix this?

Thanks,

Robin

Mixed-signal CDL netlist export

$
0
0

Hi, 

I have a mixed-signal design and I want to export this in a CDL netlist format. I have seen through the documentation that there exists a Mixed-Signal Netlisting Mode option besides Digital and Analog options. However, I do not see that former option. What kind of tool should I install in order to see the option?

FYI: I am using Virtuoso IC6.1.8

Kind regards, 

Nicolas

How to fix "*WARNING* file /home/Kaveri/CDS.log Malformed Lock-Stake file.", when running virtuoso?

$
0
0

Hi All,
When I start virtuoso, I have this message:
*WARNING* file /home/Kaveri/CDS.log Malformed Lock-Stake file. Close this program, remove Lock-Stake file manually or using clsAdminTool and restart application.
*WARNING* file /home/Kaveri/CDS.log.2 Malformed Lock-Stake file. Close this program, remove Lock-Stake file manually or using clsAdminTool and restart application.
*WARNING* file /home/Kaveri/CDS.log.3 Malformed Lock-Stake file. Close this program, remove Lock-Stake file manually or using clsAdminTool and restart application.

After waiting a few minutes, virtuoso opens up.
But, how to fix the Warnings?

Best regards,
Marben


VerilogA

$
0
0

Could anyone help me out with how to open editor to get started with VerilogA , I have chosen VerilogA in the cell view but it open up a command prompt and the keyboard dosen't seem to work alright there. 

I have attached a few pictures which makes things clearer.    

Pin placement does not show up

$
0
0

Hi Cadence Forum,

I have a large amount of pins 4000+, and I want to generate pins and attach them to the corresponding nets automatically. I want to use Place -> Pin Placement, but for some reason there is no pop-up window... I have also tried to generate all the pins and attach them by using Place -> Analog -> Adjust Cell Pins but without success (Virtuoso crashes); normally this worked with other designs. The latter approach could be performed with smaller design, but with larger design I am getting problems.

I am using IC6.1.8.

Thanks

Kind regards,

Nicolas

Plotting temperature in a transient simulation

$
0
0

I am running ic6.1.7-64b.500.23 and i am using ADE XL. 

I am changing dynamic parameter, a temperature, during transient simulation, and that works well for me. However, after sims are done and i plot signals, how do i plot temperature vs time? 

already tried all save options, tried seeing if i can find temperature in results browser, no luck. ideas?

Smooth dynamic parameter variation in transient sim

$
0
0

In a transient sim we know we can put any PWL source and if we define t1 and t2 with their corresponding values, during a sim there will be linear transition of the voltage source between that time.

if someone wants to vary the dynamic parameter (say a temperature), he can enter the temp values vs time stamps, in other words it will have to be done in discrete steps; but now, my question is, is there a way to vary some dynamic parameter in a smooth way, say if you define 27C at 1ms and 100C at 10ms, then temperature linearly rises during transient sim from 27C to 100C, rather than defining discrete steps. is there a way to achieve this?

Method to scale up or down lots of resistor/capacitor value together

$
0
0

Hi,

I encounter such a user case: I have large number of capacitors and resistors in one schematic, each with a specific capacitance or resistance value. Now I want to scale up all capacitance by X times for all caps, and scale down all resistance by Y times for all resistors. Instead of changing the value one by one, element by element, which is very time consuming, is there a way to change all of them together at once? Such as a find&replace in office word with a wild card? How can I do that?

Thanks,

cqian

Viewing all 4911 articles
Browse latest View live


<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>