Y

I picked up freepdk45 and nangate from somebody's junkyard.

Nangate is supposedly developed for freepdk, but in this case, it has its own tech file.

The LSW looks so different, what should i do to synchronize them.

Does any one know the meaning of such a sign in the data view? why it is different from others?

Hi , I'm trying to simulate a simple inverter circuit using FinFET  , I have downloaded the ASAP7_PDKandLIB and added its path in library path editor .

Now when i try to simulate it in ADE L , I'm not able to get any waveforms  . I'm getting the following error. 

ERROR (OSSHNL-116): Unable to descend into any of the views defined in the view list, 'spectre cmos_sch cmos.sch schematic veriloga', for the
instance 'M0' in cell 'inv'. Either add one of these views to the library 'finfet',
cell 'nmos_lvt' or modify the view list to contain an existing view.

End netlisting Feb 24 21:40:58 2020
ERROR (OSSHNL-514): Netlisting failed due to errors reported before. Netlist may be corrupt or may not be produced at all. Fix reported errors and netlist again.
...unsuccessful.

Any help will be most appreciated.

Thank You 

Pradeep

I have a mtline instance in a spectre netlist that looks like this.  Note dlosstype=tangent and dloss=[0.1] (so really lossy)

ITL (net1 net2 net3 net4 0 0) mtline len=100m m=1 fmax=10G linetype=stripline \
    modeltype=wideband numlayer=1 numgnd=1 er=[4.0] \
    layerthickness=[500u] linewidth=[200u] lineheight=[250u] \
    linethickness=[25u] linespace=[200u] linesigma=9e7 \
    dlosstype=tangent dloss=[0.1] gndthickness=[25u] gndsigma=9e7

In the RLCG file that spectre creates I see the following before the actual numbers.  Note that the dielectric loss settings seem to have made it but there is no "G" generated, just "RLC".

; The RLCG matrices produced by mtline 2-D field solver
; The Inputs are:

; lmgLineType = Stripline
; lmgModelType = LossyWide
; lmgNumLines = 2
; lmgDielectricPermittivity = 4
; lmgDielectricThickness = 0.0005
; lmgNumLayers = 1
; lmgDielectricLossType = tangent
; lmgDielectricLoss = 0.1
; lmgNumGndPlanes = 1
; lmgGndThickness = 2.5e-05
; lmgGndSigma = 9e+07
; lmgConductorWidth = 0.0002
; lmgConductorGaps = 0.0002
; lmgConductorThickness = 2.5e-05
; lmgConductorHeight = 0.00025
; lmgLineSigma = 9e+07
; lmgMaxFreq = 1e+10

FORMAT Freq: L1:1 L2:1 L2:2
R1:1 R2:1 R2:2
C1:1 C2:1 C2:2

am I missing something obvious?  Some other flag needed?

Thanks

-Dan

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Hello,

My cadence Virtuoso version is IC6.1.8-64b.500.9 and my Spectre simulator version is sub-version 19.1.0.237.isr3.

From my understanding sfl stands for the flicker noise of a transistor and what is the thermal noise? is it mn:sid? 

I read a note on this forum from long time ago:https://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin%3AViewSolution%3BsolutionNumber%3D11018266 but I am not sure how to determine thermal noise.

Here is what I get for an N-channel and P-channel transistors mn and mp:

Total: 18 type(s) of signals
Signal type: V Data type: Real
'mn:vds' 'mn:vgs' 'mn:vsb' 'mn:vto' 'mn:vts' 'mn:vth' 'mn:vgt' 'mn:vdss' 'mn:vearly' 'mn:lp_vfb' 'mn:lp_a2' 'mn:vbs' 'mp:vds' 'mp:vgs' 'mp:vsb' 'mp:vto' 'mp:vts' 'mp:vth' 'mp:vgt' 'mp:vdss' 'mp:vearly' 'mp:lp_vfb' 'mp:lp_a2' 'mp:vbs' 'vbn' 'vbp' 'vdn' 'vdp' 'vgn' 'vgp' 'vx'
Signal type: I Data type: Real
'mn:1' 'mn:2' 'mn:3' 'mn:4' 'mp:1' 'mp:2' 'mp:3' 'mp:4' 'vbsn:p' 'vbsp:p' 'vdsn:p' 'vdsp:p' 'vgsn:p' 'vgsp:p' 'vnoi:p'
Signal type: enum Data type: Real
'mn:region' 'mp:region'
Signal type: real Data type: Real
'mn:sdint' 'mn:vsat' 'mn:u' 'mn:sfl' 'mn:sqrtsff' 'mn:sqrtsfw' 'mn:sid' 'mn:sig' 'mn:cigid' 'mn:noi_mid' 'mn:noi_mig' 'mn:noi_migid' 'mn:noi_cgeff' 'mn:noi_cigid' 'mn:fknee' 'mn:sigs' 'mn:sigd' 'mn:siavl' 'mn:ssi' 'mn:sdi' 'mn:lp_ct' 'mn:lp_themu' 'mn:lp_cs' 'mn:lv13' 'mn:lv14' 'mn:lp_thecs' 'mn:lp_ctg' 'mn:lp_cfac' 'mn:lp_axac' 'mn:lp_alpac' 'mn:lp_gc2ov' 'mn:lp_gc3ov' 'mp:sdint' 'mp:vsat' 'mp:u' 'mp:sfl' 'mp:sqrtsff' 'mp:sqrtsfw' 'mp:sid' 'mp:sig' 'mp:cigid' 'mp:noi_mid' 'mp:noi_mig' 'mp:noi_migid' 'mp:noi_cgeff' 'mp:noi_cigid' 'mp:fknee' 'mp:sigs' 'mp:sigd' 'mp:siavl' 'mp:ssi' 'mp:sdi' 'mp:lp_ct' 'mp:lp_themu' 'mp:lp_cs' 'mp:lv13' 'mp:lv14' 'mp:lp_thecs' 'mp:lp_ctg' 'mp:lp_cfac' 'mp:lp_axac' 'mp:lp_alpac' 'mp:lp_gc2ov' 'mp:lp_gc3ov'
Signal type: A Data type: Real
'mn:ise' 'mn:ige' 'mn:ide' 'mn:ibe' 'mn:ids' 'mn:idb' 'mn:isb' 'mn:igs' 'mn:igd' 'mn:igb' 'mn:idedge' 'mn:igcs' 'mn:igcd' 'mn:iavl' 'mn:igisl' 'mn:igidl' 'mn:ijs' 'mn:ijsbot' 'mn:ijsgat' 'mn:ijssti' 'mn:ijd' 'mn:ijdbot' 'mn:ijdgat' 'mn:ijdsti' 'mp:ise' 'mp:ige' 'mp:ide' 'mp:ibe' 'mp:ids' 'mp:idb' 'mp:isb' 'mp:igs' 'mp:igd' 'mp:igb' 'mp:idedge' 'mp:igcs' 'mp:igcd' 'mp:iavl' 'mp:igisl' 'mp:igidl' 'mp:ijs' 'mp:ijsbot' 'mp:ijsgat' 'mp:ijssti' 'mp:ijd' 'mp:ijdbot' 'mp:ijdgat' 'mp:ijdsti'
Signal type: Coul Data type: Real
'mn:qg' 'mn:qd' 'mn:qb' 'mn:qs' 'mn:qgs_ov' 'mn:qgd_ov' 'mn:qfgs' 'mn:qfgd' 'mn:qgb_ov' 'mn:qjun_s' 'mn:qjun_d' 'mp:qg' 'mp:qd' 'mp:qb' 'mp:qs' 'mp:qgs_ov' 'mp:qgd_ov' 'mp:qfgs' 'mp:qfgd' 'mp:qgb_ov' 'mp:qjun_s' 'mp:qjun_d'
Signal type: W Data type: Real
'mn:pwr' 'mn:pdiss' 'mp:pwr' 'mp:pdiss'
Signal type: Ohm Data type: Real
'mn:gm' 'mn:gmb' 'mn:gds' 'mn:gjs' 'mn:gjd' 'mp:gm' 'mp:gmb' 'mp:gds' 'mp:gjs' 'mp:gjd'
Signal type: F Data type: Real
'mn:cdd' 'mn:cdg' 'mn:cds' 'mn:cdb' 'mn:cgd' 'mn:cgg' 'mn:cgs' 'mn:cgb' 'mn:csd' 'mn:csg' 'mn:css' 'mn:csb' 'mn:cbd' 'mn:cbg' 'mn:cbs' 'mn:cbb' 'mn:cgsol' 'mn:cgdol' 'mn:cgbol' 'mn:cjs' 'mn:cjsbot' 'mn:cjsgat' 'mn:cjssti' 'mn:cjd' 'mn:cjdbot' 'mn:cjdgat' 'mn:cjdsti' 'mn:lv36' 'mn:lv37' 'mn:lv38' 'mp:cdd' 'mp:cdg' 'mp:cds' 'mp:cdb' 'mp:cgd' 'mp:cgg' 'mp:cgs' 'mp:cgb' 'mp:csd' 'mp:csg' 'mp:css' 'mp:csb' 'mp:cbd' 'mp:cbg' 'mp:cbs' 'mp:cbb' 'mp:cgsol' 'mp:cgdol' 'mp:cgbol' 'mp:cjs' 'mp:cjsbot' 'mp:cjsgat' 'mp:cjssti' 'mp:cjd' 'mp:cjdbot' 'mp:cjdgat' 'mp:cjdsti' 'mp:lv36' 'mp:lv37' 'mp:lv38'
Signal type: m Data type: Real
'mn:lpoly' 'mn:lv51' 'mp:lpoly' 'mp:lv51'
Signal type: Ohm Data type: Real
'mn:rout' 'mn:rg' 'mn:lp_rs' 'mp:rout' 'mp:rg' 'mp:lp_rs'
Signal type: A_V_2 Data type: Real
'mn:beff' 'mp:beff'
Signal type: Hz Data type: Real
'mn:fug' 'mp:fug'
Signal type: A_2_Hz Data type: Real
'mn:sfledge' 'mn:sidedge' 'mp:sfledge' 'mp:sidedge'
Signal type: m_2__V_s Data type: Real
'mn:lp_betn' 'mp:lp_betn'
Signal type: m_V Data type: Real
'mn:lp_mue' 'mp:lp_mue'
Signal type: V__1 Data type: Real
'mn:lp_xcor' 'mn:lp_thesat' 'mn:lp_thesatac' 'mp:lp_xcor' 'mp:lp_thesat' 'mp:lp_thesatac'
Signal type: K Data type: Real
'mn:dtsh' 'mn:tk' 'mp:dtsh' 'mp:tk'

Hi,

I have a requirement to characterize a set of standard cells of following type : 

All of these custom cells have the same transistor arrangement, i.e. a transmission gate pair followed by an inverter. Since the inverter isolates the inputs from the loads of the cell, this cell can be characterized over a wider slew/load range. A similar example can also be found in "Liberate - Characterization Setup for Special Mux Cells" RAK (i.e. MXIUI2X1) .

However the input capacitance values after the characterization seem to be quite larger than the values I observe in my spice simulation. 

Instead of manually updating the input capacitance in the .lib file using the spice data, is it possible to automatically calculate the correct values for these type of cells using Liberate itself ?

Thanks in advance

Anuradha

Hi there,

I was running a PVS- QRC but ran into an error--ERROR (LBMISC-215294): can't open string file /tmp/strtabx45RH3 in map_file_to_strtab ().

PVS version is 15.2

The QRC is Version 13.2.0-s329.

The whole log file is:

Cadence Extraction QRC - 64-bit Parasitic Extractor - Version 13.2.0-s329
Tue Apr 15 20:11:01 PDT 2014
-----------------------------------------------------------------------------------------------------------
Copyright 2013 Cadence Design Systems, Inc.

INFO (LBRCXM-642): Constructing the RCX run script

WARNING (RCXSPIC-27104): p2lvsfile in tech directory does not have resistance
temperature coefficients (TC1, TC2). ?temperature is ignored

ERROR (LBMISC-215294): can't open string file /tmp/strtabx45RH3 in map_file_to_strtab ()

INFO (RCXSPIC-27150): The following forked command failed. Contact Cadence Customer Support for assistance.
agdsPrep -V -rundir /tmp -outdir /tmp/row_inv_x1 -sch -df2 -e /tmp/row_inv_x1.gds.map:row_inv_x1.alm,row_inv_x1.ilf -pl row_inv_x1.ports -mcell /tmp/row_inv_x1/row_inv_x1.hcl -l /tmp/row_inv_x1.lvsfile -i row_inv_x1.ixf,row_inv_x1.lph,row_inv_x1.sph:row_inv_x1.gdx -n row_inv_x1.nxf,row_inv_x1.stl:row_inv_x1.gnx -s row_inv_x1_pin_xy.spi:row_inv_x1.xcn,hccidtmfile

Forking: agdsPrep -V -rundir /tmp -outdir /tmp/row_inv_x1 -sch -df2 -e /tmp/row_inv_x1.gds.map:row_inv_x1.alm,row_inv_x1.ilf -pl row_inv_x1.ports -mcell /tmp/row_inv_x1/row_inv_x1.hcl -l /tmp/row_inv_x1.lvsfile -i row_inv_x1.ixf,row_inv_x1.lph,row_inv_x1.sph:row_inv_x1.gdx -n row_inv_x1.nxf,row_inv_x1.stl:row_inv_x1.gnx -s row_inv_x1_pin_xy.spi:row_inv_x1.xcn,hccidtmfile
ERROR (LBRCXM-644): Bad return status from RCX script generator. 0x100

INFO (LBRCXM-709): ***** QRC terminated abnormally *****

Thanks,

Yang

Hello,

Is there some way to run an stb analysis with spectre without having to edit the schematic and manually place an iprobe (or 0V source)? I am looking for a way to be able to run stability checks without editing a finished schematic or copying the view and adding a probe. 

I found this post from a number of years ago. Was this suggestion by Andrew, or an alternative, ever implemented?

Any suggestions would be appreciated.

Thanks,

Dustin

Hi,

Is it possible to set a range of voltage in transient simulation, so the simulator can dump those data only without getting the whole period of transient simulation result?

The reason I want to do that is because I only want to get the zero crossing voltage timing information, which needs to be high precision.

But setting the high precision in transient would get many useless time point at other voltage. As the simulating time increase, the data would be very large.

Thanks,

Hi,

I tried to convert a rectangular fluidgaurdring in to a polygon.

But I got a warning.

*WARNING* (LE-105557): The instance cannot be updated since the device Convert to Polygon fluid function could not be found. Check installation

please help me 

thanks,

Ganesh Doddipatla.

Hi,

I have a simple mixed signal schematic. I am running Cadence UNL netlister. I would like to see the output from the analog netlisting process. If I open the "netlist" file under analog directory, it seems it does not correctly represent the connectivity. I am working on a post-processing script that would need to parse the analog netlist of the mixed signal circuit.

Is there a way to access this file?

Regards,

Ibrahim Onur  

Hello everyone,

I had a strange problem regarding my system simulation in Cadence. My Cadence version is IC6.1.4.485. I am working on the simulation of a high-frequency PLL-based Clock and Data Recovery these days. Today, when I simulated the basic system (all blocks are transistor level), everything was ok and my results were good, but when I added some digital circuits that they are nothing to do with the basic system the output of the system changes. It is very strange because the additional circuits are not connected to the basic system. Can anybody guide me to solve my problem?

Thanks. 

I aim to make either R5(left) or R6(right) to conduct at a time. I don't understand the terminology of this switch when it says the ON voltage and the OFF voltage because when I see the operation only one of the twp voltage makes sense and the other one seems pointless. Also, please let me know what should I do to make either of one to conduct using these 2 switches. The threshold voltage is like if its 0.5V then R5 should conduct and if its -0.5V then R6 should conduct, that is simply what I want to do. This part works in LTSpice and there there is a terminology of the threshold voltage. 

`

hi,

I am trying to create the layout of my schematics. Unfortunately I have a few big capacitors and the error I get when I run DRC check is : 

M6.DN.5:L :

M6 density inside CTMDMY over any 200 um x 200 um area (checked by stepping in 100 um increments) [the overlapped area of checking window and CTMDMY >= 2500 um2] >= 0.5
DENSITY MCAPx_CTMDMY CTMDMY -lt 0.500000 -window 200.000000 200.000000 -step 100.000000 100.000000 -inside_of layer CHIPx -backup -print M6.DN.5L.density M6.DN.5:L:L266326

and I can't understand what this is about. If I make a smaller capacitor then there is no error. But if I use multiple instances of small capacitors then i get again the same error.

I've also measured CMTDMY area and is larger than two times the capacitor(metal) area. 

Hi all

I'm simulating a trimming sequence in ADE Explorer using a MDL control file. It is woking fine for corner simulation but once I run it for Monte Carlo validation, it gives me the following error:

ERROR (EXPLORER-5069): Cannot complete the Monte Carlo simulation because of the following error for the test
 ------------------------------
 The Monte Carlo analysis information is missing from the Spectre output log. Contact Cadence Customer Support to help you generate the debugging information and troubleshoot the issue.
 
 ------------------------------
Valid data not found for "trimed_word", check expression and/or filter settings.
Valid data not found for "vref_final", check expression and/or filter settings.
ERROR (WIA-1175): Cannot plot waveform signals because no waveform data is available for plotting.
One of the possible reasons can be that 'Save' check box for these signals are not selected in the Outputs Setup pane. Ensure that these check boxes are selected before you run the simulation.
ERROR (VIVA-9000):No image saved: Possible reasons could be that none of the windows
or subwindows are visible or are non-empty.

I'm saving all plot families and process parameters. I'm just curious if MDL control file configuration actually works for Monte Carlo in ADE or it have to be configured in the MDL view.

Thanks

Hello, 

I have this attached waveform that represents a frequency response of a model,

I am trying to find the frequency at where the output is maximum which represents for me the f2. the f1 I should find it as usual as for first-order circuits by multiplying the passband amplitude with 0.707 (which represent the - 3 dB), then f1 is the frequency at the resulted value.

I am trying to do it from Cadence calculator but looks like Xval function is not working,

for example Calculator is not giving me the Xval for the Ymax(Outputcap) to get f2, the same problem when trying to find f1

For your kind concern

Thank you

I'm exporting all the net voltages (for a specific time) from a circuit and I noted that if I perform the simulation with APS++ and XPS the signals are saved with the slash notation. Example:

option( ?categ 'turboOpts
    'apsplus  t
    'uniMode  "XPS MS"
)

In this case the signals are saved as:

/NET<0>

/I0/netX<0>

If I simulate with spectre only the signals are saved as:

NET\<0\>

I0.netX\<0\>

Note the \ to scape the <> too.

Is there an option to set one style or the other ?

I have installed IC617 and MMSIM151 in Ubuntu 18.04.4 LTS. Everything gose well until I start simulation and launch ADE L. Once upon I open the ADE window, a warning is thrown out.

*WARNING* The Virtuoso Analog Design Environment (ADE) creates a user interface (UI) to match the features of the particular
version of MMSIM you are using. The software could not find the 'feature file' in the MMSIM hierarchy that lists the features
available in this version of MMSIM. You might be using a wrapper script around spectre such that 'which spectre' returns
your wrapper script and not spectre in the MMSIM hierarchy. For now, ADE will create a UI to match the latest version
of spectre. If you are using an older version and do not want to see the UI for features that are not available in
that version, you can set the following variable according to spectre version you are using:
setenv SPECTRE_FEATURE_FILE /home/pathForMMSIM/tools/spectre/etc/files/spectre.dat

I followed its davice and execute the last command by:

export SPECTRE_FEATURE_FILE=/mnt/d/cadence/MMSIM/tools/spectre/etc/files/spectre.dat

However this doesn't work and once I open the ADE window, this warning continues to throw out with two error:

Loading cdf.cxt
Loading AMSPlugin.cxt
*Error* concat: illegal argument type - nil
*WARNING* (DEBASE-102079): A SKILL error occurred in function artMenuTrigger
*Error* append: argument #2 should be a list - t

I opened the stacktrace and try to figure out the problem of error, these are the stacktrace result at error:

*Error* concat: illegal argument type - nil
<<< Stack Trace >>>
(... in _amseGetCurrentSession ...)
(... in _isEdenSession ...)
(... in artiSetWindowDataDir ...)
(... in artSetWindowDataDir ...)
(... in sevSetWindowDataDir ...)
(... in sevSetSchematicEnvProperties ...)
(... in sevSetSchematic ...)
(... in sevStartSession ...)
(... in sevSchematicArtistPulldownMenus ...)
apply(artSchematicArtistPulldownMenusFunc() list(args))
let((simulatorchosen design) if(((args->window)->sevSession) then (simulatorchosen = sevSimulator(((args->window)->sevSession))) else (design = sevDesignInSchematic((args->window))) (simulatorchosen = _asiGetDefaultSimulator(car(design) cadr(design) caddr(design)))) cond(((simulatorchosen == "ams") unless(deFindPlugin('amsaAMSPlugin (args->window)) _artInstallPlugin((args->window) 'amsaAMSPlugin))) (rexMatchp("Verilog$" simulatorchosen) unless(deFindPlugin('artVerimixPlugin (args->window)) _artInstallPlugin((args->window) 'artVerimixPlugin))) (t when(deFindPlugin('artVerimixPlugin (args->window)) deRemovePlugin((args->window) 'artVerimixPlugin)) when(deFindPlugin('amsaAMSPlugin (args->window)) deRemovePlugin((args->window) 'amsaAMSPlugin)) when(deFindPlugin('ddsgHEDPlugin (args->window)) deRemovePlugin((args->window) 'ddsgHEDPlugin)))) apply(artSchematicArtistPulldownMenusFunc() list(args)))
(... in _deApplyTrigger ...)
(... in unknown ...)
funobj@0x18cde638()
(... in _dePullTrigger ...)
(... in _deCallMenuTrigger ...)
(... in unknown ...)
(... in __deMakeBannerMenus ...)
(... in __deInstallNewAppInWindow ...)
(... in __deInstallApp ...)
(... in deInstallApp ...)
deInstallApp(hiGetCurrentWindow() "analogArtist-Schematic")
*WARNING* (DEBASE-102079): A SKILL error occurred in function artMenuTrigger
*Error* append: argument #2 should be a list - t
<<< Stack Trace >>>
(... in _deCallMenuTrigger ...)
(... in unknown ...)
(... in __deMakeBannerMenus ...)
(... in __deInstallNewAppInWindow ...)
(... in __deInstallApp ...)
(... in deInstallApp ...)
deInstallApp(hiGetCurrentWindow() "analogArtist-Schematic")

It seems that the two error both comes from the 

deInstallApp(hiGetCurrentWindow() "analogArtist-Schematic")

which troubles me much since I have no idea of how to continue my debug. It would be kind of you to give me some hints or help me figure out this issue.

I have a complete layout with pads attached to it. I want to extract its netlist. Can some tell me how do i do that?