Quantcast
Channel: Cadence Custom IC Design Forum
Viewing all 4915 articles
Browse latest View live
↧

pnoise jitter and pnoise time average discrepency: what is the problem?

February 13, 2020, 10:33 am
$
0
0

Hi everyone,
I try to get the jitter from a clock generator, but I also need the phase noise curve for other reasons:
- When I simulate my circuit with the pnoise/jitter method, I get a RMS Jitter in a given bandwidth of 594.386fs (Jee>RMS).
- And when I simulate with the pnoise/time average method, by calculating my Jitter from the Phase Noise curve, I get 269.2fs.

Assuming that the pnoise>PM>Phase Noise plot is the IEEE definition, say Single-Sideband-to-Carrier Ratio, so-called L(df), "L-script of df",
I compute the RMS jitter as follows in my calculator:
[1 / sqrt(2)*pi*f0] * sqrt{ INTEGRAL[ L(df).df ] }

Of course, here L(df) is converted in linear, L(df)=10^LdBc(df)/10

In your opinion what do I miss??

Thanks a lot in advance for your help!

↧
Search

plotting noise via Matlab

February 13, 2020, 3:58 pm
$
0
0

Hello,

My cadence Virtuoso version is IC6.1.8-64b.500.9 and my Spectre simulator version is sub-version 19.1.0.237.isr3

I am working with a PSP103 transistor model. I am simulating the DC operating point via a Matlab config file that will start the spectre simulation engine. The simulation runs fine and the netlist file is generated. 

Here is my netlist file: 

community.cadence.com/.../techsweep_5F00_120psp.txt

Here is my Matlab configuration file: 

community.cadence.com/.../techsweep_5F00_config_5F00_psp_5F00_120_5F00_spectre.txt

The Thermal and flicker noise setup is from line 80-82 in techsweep_config_psp_120_spectre.txt file

c.outvars_noise = {'STH','SFL'};
c.n_noise{1}= {'mn:sid', ''};
c.n_noise{2}= {'mn:sfl', ''};

Here is the main script that calls the simulator and cds_srr

community.cadence.com/.../techsweep_5F00_config_5F00_spectre.txt

The noise simulation setup is  from line 73 to line 86 in the techsweep_config_spectre.txt file and when I run the script, I get the following error:

Simulation Starts for L = 0.120
Simulation Finished for L = 0.120 with VSB = 1.00 V
Error: The special signal is not exist.
One or more output arguments not assigned during call to "cds_innersrr".

Error in techsweep_spectre_run (line 80)
struct_n = cds_innersrr(c.outfile, c.sweep_noise, params_n{1},0);

In this forum from a long time ago, a similar question was asked: 

https://community.cadence.com/cadence_technology_forums/f/rf-design/19229/cds_srr-error

The replay was provided by the great Andrew Beckett.  "I've only seen this if either the directory name or the result dataset (second arg) is invalid for the data that exists - and then it gives a message before the error."  The result data set is valid. I may be wrong. 

"Also, I believe it may happen with non-spectre simulation results" It is a spectre simulation result. 

But when I do this: 

cds_innersrr(c.outfile, c.sweep_noise, params_n{1})
Error: The special signal is not exist.

Why is this error showing up? I have checked from PSP103p2 model summary that the flicker noise current spectral density is called "sfl" and the channel thermal noise current spectral density is called "sid".

And when I do this:

cds_innersrr(c.outfile, c.sweep_noise), I get:

Total: 40 properties
'PSFversion' 'BINPSF creation time' 'ENV_VAR_0' 'ENV_VAR_1' 'ENV_VAR_2' 'ENV_VAR_3' 'ENV_VAR_4' 'ENV_VAR_5' 'ENV_VAR_6' 'ENV_VAR_7' 'ENV_VAR_8' 'ENV_VAR_9' 'ENV_VAR_10' 'ENV_VAR_11' 'ENV_VAR_12' 'ENV_VAR_13' 'PSF style' 'PSF types' 'PSF sweeps' 'PSF sweep points' 'PSF sweep min' 'PSF sweep max' 'PSF groups' 'PSF traces' 'simulator' 'version' 'date' 'design' 'analysis type' 'analysis name' 'analysis description' 'xVecSorted' 'tolerance.relative' 'operating point producer' 'output' 'output probe' 'output probe type' 'ground' 'positive output signal' 'negative output signal'

Total: 1 type(s) of signals
Signal type: A_sqrt_Hz_ Data type: Real
'out'


ans =

struct with fields:

signal_info: {'prop' 'Unknown' 'A_sqrt_Hz_' 'Real'}
prop: {40×1 cell}
A_sqrt_Hz_: {'out'}

I do not know what I am doing wrong?

Thank you so much indeed.

↧
↧

Specifying Operating Region Expressions Using the Operating Region Assistant Pane in ADEXL

February 14, 2020, 3:50 am
$
0
0

Hello, 

I am using Cadence Virtuoso version IC6.1.6

I am facing little problem when I try to operating region specification to my output setup in ADEXL,

when click to add the operating point  spec for my test, I will be transferred to the next window where "Operating Region Assistant Pane".  it is supposed from this pane that I can click on the instance to "show Parameter" as proposed in the help documentation. However, for my case this tab will not appear after selecting the instance, beside that, the "Sub" tab is not recognizing the circuit as you can see from the image. I am saving the DC operating point in the DC analyses before going in this procedure.

I am performing it alternatively by using the "Show All" then using the "Advanced" option, but I would prefer to use the former method as it more friendly to select the instance by clicking on it.

My second relevant question, I want to save the region of the transistor as an operating point, and I want to check for region 2, however, there is no option in the expression that I can use for "equal" nor a "Range" to put it in between, 

this problem can be extended to other parameters, like if I want to check if the current is between 50 uA and 70 uA, ?

The last but not the least, when the operating point are added in to the output setup, there is a specification fixed to < 1, what this mean ?

I do appreciate your help in this manner

Best Regards

↧

sp1tswitch equivalent for pac simulations

February 14, 2020, 8:22 am
$
0
0

Hi everyone,

in spectre is there an equivalent of the sp*tswitch to be used in a pac simulation?
For example, in an AC simulation, the sp1tswitch break a circuit in AC mode only, while for the DC point of view the switch is a short.
Can I do the same thing in a PAC simulation? I.e. keeping the switch a short for the PSS simulation while being an open for PAC only and viceversa?
Thank you,

Nicola

↧

How to increase font size of plots axis labels & markers in Cadence virtuoso

February 14, 2020, 5:01 pm
$
0
0

Hi,

What env variables to change when I want to increase the font size of plot axis labels and markers in Cadence virtuoso?

↧
↧

How to do advanced Analysis in ADE XL GUI

February 15, 2020, 12:25 am
$
0
0

Hello,

Is it possible to do advanced sweep analysis using the GUI in cadence virtuoso ADE XL?

To be specific I am able to launch spectre simulation from a command line using spectre netlist as in the attached example called nfet_char.scs

community.cadence.com/.../nfet_5F00_char.txt

I have read spectreuser pdf documentation starting page 349 under Advanced Analysis (sweep and montecarlo) but it doesn’t specify how to perform this type of simulation in the ADEXL GUI.

Thank you so much in advance.

↧

How to add mismatch to Monte Carlo design variables?

February 15, 2020, 8:29 pm
↧

Jop policy setting in ADEXL

February 16, 2020, 8:39 am
$
0
0

Hello,

Is the number of " Max job" in job policy setting / ADEXL has a relationship to the number of tests?  or should I leave it always by default to 1 ?

Indeed I read the help documentation about it but couldn't understand how to perfectly setting it

Thank you in advance

↧
Search

Cadence Pegasus or PVS

February 17, 2020, 3:18 am
$
0
0

I had worked on Cadence Assura platform. Currently for a new project we are upgrading to new version of the tool chain. Our design complexity is similar to a multi core SoC. While looking for the tools for physical verification I came across Cadence PVS and Cadence Pegasus platforms.

Can you please advice me on which is best suited for out project, Cadence PVS or Cadence Pegasus, in terms of support (RDK's, GPDKs, training materials, fab support etc).

Thanks and Regards

   Varun M J

↧
↧

DSPF file disregard in extracted simulation

February 17, 2020, 9:42 am
$
0
0

Hi everybody,

I need some guidelines to debug a dspf related issue. The devices in my dspf file created with Calibre xACT are not recognized by spectre. I've done countless parastiic extraction simulation with this workflow and I do not find where things went wrong or what I did differently. I've run successfully extracted simulations with the given dspf file and it was under version control. There was no change in any Cadence environment I am aware of. I have no clue what went wrong.

Issue: There are "element not found" and "node not found. Net is not expanded" errors in the input.spe.spfrpt file. The log pointed me to this file.

ERROR  (STITCH-0040)(:462) :  Element xbufp.xmn0@4 not found.
ERROR  (STITCH-0000)(:164) :  Node vss not found. Net is not expanded
** In NET "tank_n" (:168) ** :

I got no additional info by enabling info and debug in ADE L's Options->Analog forms.

My questions:

  1. Is it possible to force spectre to use the dspf file as 'the' netlist. So no backannotation, no stitching, just a simulation with a pure netlist without information about the schematic. (Workaround)
  2. How could I debug further what went wrong? How can I check what names does spectre expect? The layout was LVS clean, which is a requirement of a parasitic extraction.

I am using mmsim 19.10.063 on icadv 12.3.

Thanks!
Zoltan

PS:

A slightly related question: Why do I got different printing in the output log when I load the dspf file through ADE L/Simualtion Files/DSPF or with spf="<dspf file>" analysis option?

I have originally included the dspf file through ADE L's Setup/Simulation Files/DSPF section. In the output log it writes the following:

Warning from spectre during circuit read-in.
    WARNING (SFE-2957): No schematic subckt definition is available, spf port order is used.

Later I tried to add the dspf inclusion as an option based on Spectre's User Guide spf="<dspf file path>". In that case a "PARASITIC BACK-ANNOTATION SUMMARY" is shown in the output. Here I see that nodes and instances were not found. My understanding was that the two methods to define a dspf file for stitching is equivalent.

↧

Improve Yield is not running,

February 18, 2020, 10:02 am
$
0
0

Hello, 

I am using Cadence Virtuoso version IC6.1.6

I am trying to run the "Improve Yield" from Virtuoso ADGXL after I successfully finished with the corners and montecarlo simulations. after completing the setup of the Improve Yield and hit the run, the software wait for a seconds before it terminates it with the attached reports,

community.cadence.com/.../Log_5F00_file.pdf

by the way, I run the global and the local optimization smoothly with no error

thank you in advance 

Regards

↧

FreePDK15 setup/layout problem

February 18, 2020, 11:54 pm
$
0
0

Hi, dear all,

I am trying to develop a library using FreePDK15 open cell library. But currently I can not create any vias in the layout editor and error pops up as follows when I try to add any vias.

The error is the same for all other constraint groups. 

I found a file called "FreePDK.tf" which contains a section like this. 

Are the sections standardViaDefs and customViaDefs useful? Do I have to define my own vias here? If yes, I am confused by the required inputs like "LibName" "CellName" and "resistancePerCut" so I hope someone can guide me through what should I fill for them. If not, can anyone help me find a way to define vias in the constraint group? Thanks a lot in advance!

Sincerely

Greeny 

↧

Compare two LEF files

February 19, 2020, 12:41 am
$
0
0

Hi all,

Is there any way I can compare 2 LEF files with each other?

Best regards,

Huy Hoang

↧
↧

Spectre: is it possible to specify initial conditions for DSPF blocks?

February 19, 2020, 6:00 am
$
0
0

Hi! I am in the need of simulating extracted layouts in DSPF format. They are smaller and simulate faster than other alternatives (e.g. av_extracted, calibreview). However, I can't figure out how set initial conditions for nets within the blocks described by the DSPF netlists, an without those the whole simulation is ruined (we have some servo loops that need to be initialized close to their expected solution). Is there anyway this can be done?

Thanks and regards,

Jorge.

↧

Cannot plot most terminal currents (transient)

February 19, 2020, 6:33 am
$
0
0

For devices from our foundry's PDK, I cannot plot transistor terminal currents. I can plot at least one type of resistor terminal current.

To make this simpler, I cannot plot terminal currents for the analogLib ideal resistor (res).

Under Outputs->Save All, I have saved all signals, power signals and device currents. The subcircuit probe level is set to 10.

I select the terminal current in the calculator, using the tran tab, and 'it'. This puts the current in the stack:

IT("/R33/PLUS")

When I click Eval, I get this error:

Evaluation error(Unknown scalar data type: nil). Expression: IT("/REE/PLUS")

I'm using Virtuoso ADE 5.10.41.500.6.149

Any help will be greatly appreciated.

Steve

↧
Search

current measure statement

February 19, 2020, 9:43 am
$
0
0

Hi

What is wrong with the following statement;-

.meas tran ir0 find i(Ibot.Iarray.Il.I128.Il.I0_7.Itr.N0:s) at=6n

When i use this it keeps saying the following:-

WARNING (MDL-358): ......meas" 6: probe 'I( Ibot.Iarray.Il.I128.Il.I0_7.Itr.XN0.s:1 )' is invalid.

I am using Spectre (R) Circuit Simulator Version 19.1.0.237.isr3 64bit -- 3 Jan 2020

Thanks

WB

↧

Calculator stack--swap? dup?

February 19, 2020, 11:50 am
$
0
0

Are there stack commands like swap and dup hidden somewhere?

I'd swear there used to be.

Steve

↧
↧

EvalType in Cadence ADEXL

February 20, 2020, 3:48 am
$
0
0

Hello,

I read the help documentation of ADEXL couldn't understand what the function of EvalType in the Output Setup of ADEXL interface. Basically it give two options: Point and Corners, by default Cadence set it to Point but what either means to choose the proper selection

Thank you

↧

Global net name mapping for spectre netlist

February 20, 2020, 5:05 am
$
0
0

Hi,

I have generated a spectre netlist where it has below global nets.

global 0 vss! vdd!

Now, I want to get rid off the "!" sign and want something like "global 0 vdd vss" to appear it in my spectre netlist.

I have explored a bit and found with added below lines in .simrc , it does what I want exactly.

"hnlMapNetInName = list(list("+" nil) list("(" nil) list(")" nil) list("," nil) list("/" nil) list("." nil) list("$" nil) list("[" nil) list("]" nil) list("<" "[") list(">" "]") list("!" nil) )"

But the above method works for CDL netlist. 

Is there any way to get similar thing done in spectre netlist also ?

Thanks In Advance!

Regards,

Amar

↧

Determining the sings for the DC Operating Points in ADE XL

February 20, 2020, 10:00 pm
$
0
0

Hello,

I am using cadence virtuoso version: IC6.1.8-64b.500.9 and Spectre Version: 19.1.0.237.isr3 

I would like to determine the sign for PSP103 model Operating Point Parameters such as:

Ids, vth, igd, igs, gm, gmb, cdd, cdg, cds, cdb, cgd, cgg, cgs, cgb, csd, csg, css, csb, cgsol, cgdol, cgbol, cjd, cjs for both NMOS and PMOS transistors

What I did was, I went ADE XL output panel result > print > DC Operating Points and clicked on the particular transistor.

Is that the correct way?

Thank you so much in advance. 

↧
Viewing all 4915 articles
Browse latest View live
Search
<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>