Accessing data vector generated by a Virtuoso expression in Matlab using adeInfo

February 3, 2020, 6:36 pm

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Hi,

I have been using the improved Virtuoso integration with Matlab (adeInfo etc) (Matlab R2019B, Virtuoso 18.1)

I am able to get a waveform from the results database into Matlab for processing ( i.e. of the form VT('/net_name') ) and operate on the ".y" and ".x" vectors in Matlab.

..However I have hit a snag trying to get a Cadence "Expression" Output into Matlab.

The expression I have in Cadence is a few wave processing functions (clip, sample, DFT) and results in a magnitude vs frequency vector in the output pane called "clipped_sinc_out_spectrum".

l have not been able to pass this vector into my Matlab function as an argument, either through the "Matlab Expression" feature in the outputs, or through playing about in the Matlab command prompt.

Below is the closest I have got, but it just yields that the Result is a {'wave'}, but I don't know how to access the wave data itself to start working with it?

adeInfo.adeRDB.query('constraints', Output() == 'clipped_sinc_out_spectrum' & Corner == 'Analog_TTGTT')

Thanks in advance!

Best Regards

Craig

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VAR function output slowly

February 4, 2020, 8:53 am

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I am using VAR function to get the design variable, but the output generate very slowly.

modeling output impedance in a file

February 4, 2020, 10:51 am

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hello,

i am trying to model an LDO as a norton equivalent network.  i can run an .ac simulation to get the output impedance vs frequency and export it as a file, but am having a difficult time figuring out how to attach this file (with magnitude/phase information) to a current source and then use that norton equivalent network in my simulations.  i was hoping it would be something akin to including a noise file for a vdc source, but i haven't found a way to do so.  is this even possible?

many thanks in advance.

floating metal check in layout

February 4, 2020, 5:24 pm

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hello experts,

is there some LVS/DRC/ERC checking that we can identify floating metals which doesn't connect to any pins nor devices? looks like ERC only checking floating devices but not the metal itself.

thanks,

David

avoid local alteration on iterative instances

February 6, 2020, 2:34 am

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hello,

I am running a monte carlo simulation (local mismatch only) and I would like to skip local alteration on iterative instances. 

for example, let us consider a current mirror Imaster<2:1> to Islave<4:1>.  I am interested in treating this mirror as 2 devices only (same as it would be when using m=2 and m=4 parameters) and do not apply local alteration between iterative instance, eg. bteween Imaster<2> and Imaster<1>, since these instance are anyway connected in parallel.

background of the question is to reduce simulation time, due to large input file generation when calling a monte carlo simulation on large circuits where many iterative instances are used. 

thanks, 

Giovanni

Transient Violations taking too much disk space

February 7, 2020, 8:20 am

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Hello,

I am sure this may have come up before but couldn't find this specific thing on the forums.

I am trying to run a PLL simulation using transient (liberal) and currently taking up too much space.

The file taking up most of the space is not the net outputs but rather a file called tranViolations.violations which is about 5times bigger. The simulation has a lot of voltage spikes which is most likely causing this but not really important to have this data saved. The output data seems sensible and as expected but the simulation keeps running out of disk space before finishing.

Is there a way to stop the simulator writing anything other than the selected net data?

Details of environment below:

Cadence IC Design version IC6.1.8-64b.500.4

Simulator: Spectre with APS Multhreading manual =4 threads.

Environment: ADE Assembler

Let me know if you need any further information.

Many Thanks,

Chris.

ADE L problem

February 7, 2020, 5:23 pm

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Hello,

I am trying to use ADE L to run DC and AC simulation, but when I click "analyses" => "choose", it shows the following error:

*Error* (Default-reader-method) generic:asiGetField class:list

my virtuoso version is ic-6.17.710

Thank you!

Libraries not imported in the Library manager

February 8, 2020, 2:01 am

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Dear guys，

I would like to ask a question about the libraries. When we installed Cadence before, the libraries are all well imported. But recently, it seems the following instruction in the "cds.lib" does not work:

SOFTINCLUDE $UCDPRJDIR/.ukcds5/${UK_CDS_PREFIX}cds.lib

Our current version is Cadence 6.1.7. Is it possible that this is not compatible with this version? Thanks in advance for your help.

Best regards,

UU

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cross probing between layout and schematic

February 9, 2020, 6:29 pm

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Hello

I am using Calibre , start RVE, load svdb. I'd like to be able to select devices or nets in schematic and have them highlight in the layout. How can this be done in RVE? Right now the net highlighting works only as far as zooming to the particular location of the net in the layout goes (doesn't really highlight the net in the layout).

And I am not able to highlight devices as I am being asked for a "prefix" and not quite sure what to enter there.

Thanks 

Haritha

annotating parasitics from Calibre PEX netlist to layout or schematic

February 9, 2020, 6:35 pm

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Hello,

If it is possible to cross-annotate parasitic net R, C (coupling cap Cc between nets and C from net to gnd) using Calibre PEX, would someone please tell me how to do so?

Thanks

Haritha

noise/jitter transfer function along clock-driven inverter chain

February 10, 2020, 11:21 am

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Hi everyone, hope the section is correct.

I'm simulating with spectre the inverter chain shown in the figure below where the input signal is a 30GHz sinusoid that is AC coupled to first inverter. My goal is to investigate its noise.
x6, x12... is the multiplicity of the inverters. What I want to do is to check how the noise coming from the fiirst inverter only is propagated along the chain and transformed into jitter on node N1 to node N4. 
To furthermore simplify I went to Simulation -> Options -> Analog and I checked "Noise Contribution" to On, specifying the first inverter only as noise contributor (thermal).

I set up the PSS simulation with Beat Frequency 30GHz and 10 harmonics.

**netlist**
pss pss fund=30G harms=10 errpreset=conservative autosteady=yes
+ annotate=status

Then the pnoise: since it is a periodic simulation, it's sufficient to check the noise up to half the PSS Beat Frequency. Output Freq Range is absolute and set to 10k to 15G, as seen in the picture. At every node, there will be the folding of every noise bandwidth around the harmonics of the PSS toward the 10k-15G bandwidth. But I want to simplify even more, choosing Sidebands 15G-30G and 30G-45G only in the pnoise Sidebands form. This is to check how the noise placed around the 30GHz harmonic only contributes to noise. Finally, since it's a jitter simulation, I set "Noise Type" to "sampled(jitter)", "Timing Event" to "Edge Crossing" and set a measure for each transition of N1-N4 nodes using as trigger the same measured signal (e.g. measure N1 has the same N1 signal as trigger).

**netlist**
pnoise pnoise start=10k stop=15G dec=5 sidebands=[-1 1] noisetype=sampled \
sampleratio=1 measurement=[pm0 pm1 pm2 pm3] annotate=status
pm0 jitterevent trigger=[N4 0] triggerthresh=0.45 \
triggerdir=rise target=[N4 0]
pm1 jitterevent trigger=[N3 0] triggerthresh=0.45 \
triggerdir=rise target=[N3 0]
pm2 jitterevent trigger=[N2 0] triggerthresh=0.45 \
triggerdir=rise target=[N2 0]
pm3 jitterevent trigger=[N1 0] triggerthresh=0.45 \
triggerdir=rise target=[N1 0]

What I get from the results are the following time waveforms (N1 red... N4 green).

Then if I calculate the Jee integrated from 10k to 15G I see that is always increasing along the chain from 42f to 47f.
However, if instead of Jee I plot the Output Noise spectrum I get the following behavior, with the same Node-Color relation as before: N4 output noise is lower than the N3 output noise!
How is that possible?

So here's my questions:
1) how is that possible that noise is decreasing along the chain?
2) I'd like to plot the noise transfer functions along the chain: for example, how the noise in N1 in the bandwidth 15G-30G is going to N4 noise bandwidth 0-15G. What is the best way to have such a transfer function? I tried to use the PAC sampled and also the PXF sampled, but I am not sure how to combine the results to get the sort of "flat gain" that I see in the noise spectrums above, e.g the 53.5/35.3 ~ 1.52 "voltage gain" between N1 and N4.

Thank you in advance.

Nicola

Stability check issue during phase starting with 0 degree

February 11, 2020, 12:12 am

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Hi! 

I'm trying to design buffer amp for specific application, so I want to check stability such as phase margin using an instance 'iprobe'(actually it doesn't matter to use ac simulation). However, the loop gain phase plot of the circuit starts with 0 instead of 180 deg and it's unexpected plot. I think it could be related with positive feedback or multi loops, but I'm not sure about it. The transient result of the circuit works well, but I want to check the figure of phase. Could you please help me? How can I make it clear?

Thanks.

phase noise/vin vs. frequency

February 11, 2020, 6:12 am

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Hi all,

I have a Phase Interpolator to simulate in Periodic Steady-State (shooting). This circuit synthesizes a clock with digitally-controlled delay on its ouput based on input reference clocks.

I would like to simulate the output phase noise / input phase noise transfer function (this could be either the input reference clock or VDD for PSRR) in a Bode diagram (over frequency); could somebody explain to me the way to do that ? I I know how to do for a voltage output / voltage input transfer function using PXF analysis, or simulating the intrinsic phase noise using PNOISE, but not for outpout phase noise / input phase noise transfer function...

Thanks a lot in advance.

PS: I am using Spectre with ADE-XL.

Does MC mismatch simulation reflect best or arbitrary layout ?

February 11, 2020, 6:18 am

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Hi,

one question regarding MonteCarlo (MC) mismatch simulations is, how the simulation results are related to layout.

1. Does the mismatch simulation reflect the case where the layout is optimized regarding mismatch (e.g. best common centroid layout approach + dummies) ? In this case, a non-optimum layout would cause more/bigger mismatch than simulated.
2. Or does the mismatch  simulation reflect the case of arbitrary placed components all over the wafer (or over a certain layout area)? In this case, an optimized layout (centroid + dummies, etc.) would cause less mismatch than simulated.

For example, if one designs a R2R-DAC and the mismatch-simulation shows that all specifications are fulfilled.

Would a straight forward compact layout (with dummies etc.) be good enough - or does only a best-optimized common centroid layout guarantee these results ?

BR

HoWei

How to properly shutdown virtuoso?

February 11, 2020, 7:18 am

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I mean the cds.log, virtuoso.conf, simulstion, and everything.

Cdsnameserver, clsbd process, etc.

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Save VHDL variables of specific hierachy

February 11, 2020, 10:03 am

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Hello,

I'd like to save all VHDL variables in ADE Assembler of a VHDL file in an transient AMS simulation.

The VHDL file is referenced inside a verilogams wrapper and marked as "External HDL" in the config view of the testbench.

How is it possible to save all variables in this specific subcircuit / VHDL file?

When I save all nets (Outputs -> save all... -> Save nets -> all), the variables are saved. However, this saves also all analog nets, which results in a huge simulation result and is not an option.

monte carlo simulation

February 12, 2020, 4:37 am

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Hi, 

For monte carlo simulation, all devices are treated as uncorrelated.

there is constraint manager in IC61x to set constraint coefficient between devices, for example OP input stages.

is there simulation flow to import constraint coefficient into monte carlo simulation? 

thanks.

BR,

-nathan

Reading from a file in Verilog-A

February 12, 2020, 12:45 pm

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 Dear All,

To simulate the performance of an analog IC  design (using spectre) , I want to "pass" a specific, predefined, sequence of binary data. For this purpose, I have created a "memory" using VerilogA, which outputs bits at each clock cycle. The example bellow is only for 1 bit. The idea is to load the data sequence from a separate file.

// VerilogA for RTL, memory, veriloga

`include "constants.vams"
`include "disciplines.vams"

module memory(clk, out);

input clk;
output out;
electrical out, clk;

parameter real vtrans = 0.45, high =0.9, td = 2p, tr=2p, tf = 2p;

integer fileHandle;
integer decimal_output;
integer captured_data;
integer x;

analog begin

@ (initial_step)
fileHandle = $fopen("~/bit0");
@ (final_step)
$fclose(fileHandle);
@ (cross (V(clk) - vtrans,+1)) begin
decimal_output = $fscanf(fileHandle,"%d", captured_data);
x = ( captured_data > vtrans);
end

V(out) <+ transition( high*x,td, tr, tf );

end

endmodule

The issue is that, after building, I get the following error in the "Parser Error/Warnings" window:

memory.va (/...../memory.va)

ERR741 [30:27]: Digital or unknown system function '$fscanf' found in analog
block.
</...../memory.va> : Failed with errors (1).

Do you have any toughs on this?

Virtuoso version IC6.1.7-64b.500.23

Question on ADE Assembler (maestro) corner setup

February 12, 2020, 1:48 pm

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Hi,

Could I ask in maestro, how to move design vairables in the corner setup up and down to re-sort them? I know I can delete all variables and rebuilt from scratch or modify the sequence in csv files and overwrite the corner setup. But both of these methods are very time-consuming and painful when I have many corners with many design variables.

For instance, as shown below, vdd is above freq. I want to move freq above vdd. What should I do besides rebuilding the corner setup? 

Thanks,

Yi

What is thermal noise called

February 13, 2020, 5:21 am

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Hello,

My cadence Virtuoso version is IC6.1.8-64b.500.9 and my Spectre simulator version is sub-version 19.1.0.237.isr3.

From my understanding sfl stands for the flicker noise of a transistor and what is the thermal noise? is it mn:sid? 

I read a note on this forum from long time ago:https://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin%3AViewSolution%3BsolutionNumber%3D11018266 but I am not sure how to determine thermal noise.

Here is what I get for an N-channel and P-channel transistors mn and mp:

Total: 18 type(s) of signals
Signal type: V Data type: Real
'mn:vds' 'mn:vgs' 'mn:vsb' 'mn:vto' 'mn:vts' 'mn:vth' 'mn:vgt' 'mn:vdss' 'mn:vearly' 'mn:lp_vfb' 'mn:lp_a2' 'mn:vbs' 'mp:vds' 'mp:vgs' 'mp:vsb' 'mp:vto' 'mp:vts' 'mp:vth' 'mp:vgt' 'mp:vdss' 'mp:vearly' 'mp:lp_vfb' 'mp:lp_a2' 'mp:vbs' 'vbn' 'vbp' 'vdn' 'vdp' 'vgn' 'vgp' 'vx'
Signal type: I Data type: Real
'mn:1' 'mn:2' 'mn:3' 'mn:4' 'mp:1' 'mp:2' 'mp:3' 'mp:4' 'vbsn:p' 'vbsp:p' 'vdsn:p' 'vdsp:p' 'vgsn:p' 'vgsp:p' 'vnoi:p'
Signal type: enum Data type: Real
'mn:region' 'mp:region'
Signal type: real Data type: Real
'mn:sdint' 'mn:vsat' 'mn:u' 'mn:sfl' 'mn:sqrtsff' 'mn:sqrtsfw' 'mn:sid' 'mn:sig' 'mn:cigid' 'mn:noi_mid' 'mn:noi_mig' 'mn:noi_migid' 'mn:noi_cgeff' 'mn:noi_cigid' 'mn:fknee' 'mn:sigs' 'mn:sigd' 'mn:siavl' 'mn:ssi' 'mn:sdi' 'mn:lp_ct' 'mn:lp_themu' 'mn:lp_cs' 'mn:lv13' 'mn:lv14' 'mn:lp_thecs' 'mn:lp_ctg' 'mn:lp_cfac' 'mn:lp_axac' 'mn:lp_alpac' 'mn:lp_gc2ov' 'mn:lp_gc3ov' 'mp:sdint' 'mp:vsat' 'mp:u' 'mp:sfl' 'mp:sqrtsff' 'mp:sqrtsfw' 'mp:sid' 'mp:sig' 'mp:cigid' 'mp:noi_mid' 'mp:noi_mig' 'mp:noi_migid' 'mp:noi_cgeff' 'mp:noi_cigid' 'mp:fknee' 'mp:sigs' 'mp:sigd' 'mp:siavl' 'mp:ssi' 'mp:sdi' 'mp:lp_ct' 'mp:lp_themu' 'mp:lp_cs' 'mp:lv13' 'mp:lv14' 'mp:lp_thecs' 'mp:lp_ctg' 'mp:lp_cfac' 'mp:lp_axac' 'mp:lp_alpac' 'mp:lp_gc2ov' 'mp:lp_gc3ov'
Signal type: A Data type: Real
'mn:ise' 'mn:ige' 'mn:ide' 'mn:ibe' 'mn:ids' 'mn:idb' 'mn:isb' 'mn:igs' 'mn:igd' 'mn:igb' 'mn:idedge' 'mn:igcs' 'mn:igcd' 'mn:iavl' 'mn:igisl' 'mn:igidl' 'mn:ijs' 'mn:ijsbot' 'mn:ijsgat' 'mn:ijssti' 'mn:ijd' 'mn:ijdbot' 'mn:ijdgat' 'mn:ijdsti' 'mp:ise' 'mp:ige' 'mp:ide' 'mp:ibe' 'mp:ids' 'mp:idb' 'mp:isb' 'mp:igs' 'mp:igd' 'mp:igb' 'mp:idedge' 'mp:igcs' 'mp:igcd' 'mp:iavl' 'mp:igisl' 'mp:igidl' 'mp:ijs' 'mp:ijsbot' 'mp:ijsgat' 'mp:ijssti' 'mp:ijd' 'mp:ijdbot' 'mp:ijdgat' 'mp:ijdsti'
Signal type: Coul Data type: Real
'mn:qg' 'mn:qd' 'mn:qb' 'mn:qs' 'mn:qgs_ov' 'mn:qgd_ov' 'mn:qfgs' 'mn:qfgd' 'mn:qgb_ov' 'mn:qjun_s' 'mn:qjun_d' 'mp:qg' 'mp:qd' 'mp:qb' 'mp:qs' 'mp:qgs_ov' 'mp:qgd_ov' 'mp:qfgs' 'mp:qfgd' 'mp:qgb_ov' 'mp:qjun_s' 'mp:qjun_d'
Signal type: W Data type: Real
'mn:pwr' 'mn:pdiss' 'mp:pwr' 'mp:pdiss'
Signal type: Ohm Data type: Real
'mn:gm' 'mn:gmb' 'mn:gds' 'mn:gjs' 'mn:gjd' 'mp:gm' 'mp:gmb' 'mp:gds' 'mp:gjs' 'mp:gjd'
Signal type: F Data type: Real
'mn:cdd' 'mn:cdg' 'mn:cds' 'mn:cdb' 'mn:cgd' 'mn:cgg' 'mn:cgs' 'mn:cgb' 'mn:csd' 'mn:csg' 'mn:css' 'mn:csb' 'mn:cbd' 'mn:cbg' 'mn:cbs' 'mn:cbb' 'mn:cgsol' 'mn:cgdol' 'mn:cgbol' 'mn:cjs' 'mn:cjsbot' 'mn:cjsgat' 'mn:cjssti' 'mn:cjd' 'mn:cjdbot' 'mn:cjdgat' 'mn:cjdsti' 'mn:lv36' 'mn:lv37' 'mn:lv38' 'mp:cdd' 'mp:cdg' 'mp:cds' 'mp:cdb' 'mp:cgd' 'mp:cgg' 'mp:cgs' 'mp:cgb' 'mp:csd' 'mp:csg' 'mp:css' 'mp:csb' 'mp:cbd' 'mp:cbg' 'mp:cbs' 'mp:cbb' 'mp:cgsol' 'mp:cgdol' 'mp:cgbol' 'mp:cjs' 'mp:cjsbot' 'mp:cjsgat' 'mp:cjssti' 'mp:cjd' 'mp:cjdbot' 'mp:cjdgat' 'mp:cjdsti' 'mp:lv36' 'mp:lv37' 'mp:lv38'
Signal type: m Data type: Real
'mn:lpoly' 'mn:lv51' 'mp:lpoly' 'mp:lv51'
Signal type: Ohm Data type: Real
'mn:rout' 'mn:rg' 'mn:lp_rs' 'mp:rout' 'mp:rg' 'mp:lp_rs'
Signal type: A_V_2 Data type: Real
'mn:beff' 'mp:beff'
Signal type: Hz Data type: Real
'mn:fug' 'mp:fug'
Signal type: A_2_Hz Data type: Real
'mn:sfledge' 'mn:sidedge' 'mp:sfledge' 'mp:sidedge'
Signal type: m_2__V_s Data type: Real
'mn:lp_betn' 'mp:lp_betn'
Signal type: m_V Data type: Real
'mn:lp_mue' 'mp:lp_mue'
Signal type: V__1 Data type: Real
'mn:lp_xcor' 'mn:lp_thesat' 'mn:lp_thesatac' 'mp:lp_xcor' 'mp:lp_thesat' 'mp:lp_thesatac'
Signal type: K Data type: Real
'mn:dtsh' 'mn:tk' 'mp:dtsh' 'mp:tk'