Hi.
I want to include a pwl file.
If there is one pwl source in the file, the value of the pwl file is output as voltage using 'vsource' in 'analogLib'. Already I know this.
If there are 100 pwl sources in the file, how can I output the voltage??
Thanks in advance.
Hello,
I am trying to run a pnoise jitter simulation in ADE Explorer (in Virtuoso ICADV12.3-64b) and I am encountering an issue when sweeping across corners.
When I run a single point I am able to get the desired waveform using the expression drplJitter(?result "pnoise_pmjitter" ?unit "Second" ?k 1 ?event 0)
However as soon as I try to run a sweep or corners simulation I get the following error
expression evaluation failed: drplJitter(?result "pnoise_pmjitter" ?unit "Second" ?k 1 ?event 0)
ERROR (WIA-1175): Cannot plot waveform signals because no waveform data is available for plotting.
One of the possible reasons can be that 'Save' check box for these signals are not selected in the Outputs Setup pane. Ensure that these check boxes are selected before you run the simulation
I was able to narrow down the issue to the saved results:
in single point mode, after opening the results with openResulrs("path/to/psf") results() returns:
(pss_td pss_fd pnoise_pmjitter variables)
When I do a sweep results() returns
(pss_td pss_fd pnoise pnoise_sb variables)
with no pnoise_pmjitter result. [The only difference between the 2 is if I do a single point vs 2 corners, nothing else changed]
I could not find any save option parameter that could be ticked to have pnoise_pmjitter saved as part of the results when running sweeps/corners.
Does anyone have an idea how to fix this?
Thanks in advance,
Martin
Hello,
I am trying to verify my design against PVT by running the worst case corners. I have found that I can define my corners in two methods in ADEXL:
1. From Single Run, Sweep and Corners : I can define my corners and run the simulation
2. From Creat Worst Case Corners
What are the difference in between? and which one should be the best.
I am using Cadence Virtuoso IC6.1.5
Thank you
1. Circuit
I am analysing the stability for a ciruit in cadence by breaking the feedback loop. For stability analysis we have to find the Loop gain which is A(s)B, where B is beta factor
A(s) = Adc/((s/po)+1) - single pole opamp system
The above circuit has a loog gain
AB = ((Adc*Cf*Ron*po)s + Adc*po)/ (s^2(Ron*(Cin+Cf)) + s((Ron*po)*(Cin+Cf) + 1) + po)
This has 2 poles and 1 zero
P1 = -po
P2 = - 1/(Ron) *(Cin+Cf))
Z = - 1/(Ron) *Cf)
These equations were verified in matlab and the simulations were matching with the calculation now
2. Modified Circuit
Now the same circuit is modified with a switch added with the resistor Ron.
The switching wave is given below.
Now during ton, the Loop gain (AB) is same as before (including Ron, since the switch is closed). But during toff, the Ron is inneffective and the loop gain is changed as shown below
AB = (Adc*Cf*po)/ s(Cin+Cf)) + (Cin+Cf) *po
There is only one pole now
P = -po
But how can I comeup with an overall transfer function considering the swtching waveform. That means for ton, I should have the same transfer function as case1 and during toff should have the transfer function as case2. Also, the switching wave is periodic with period = ton + toff.
If someone know this how to model the transfer function, it will be helpful. Because, the stability analysis shows diferent results for both cases. I assume that this is due to the two different transfer functions.
Hi
I want develope basic circuit of DC motor which consist of resistor, inductor and back emf in capture and check its simulation in pspice, for reference I have attached image and link.
can some tell me how to put formulas and what parameters to be set in properties get waveform as per below link.
https://www.precisionmicrodrives.com/content/ab-025-using-spice-to-model-dc-motors/ .
Hi,
During SP analysis of LNA circuit (quite large netlist due to extracted views), the simulation is very slow. I could trace it to a file (sp.noise.sp) in psf folder, which I believe gets written after SP calculation at every frequency and hence gets very large in size(~2GB). What is the purpose of this file? Does it write noise summary of each instance in that file? If I want to simulate only noise figure and not care about noise summary, how can I avoid writing to such a file, and hence speed up my SP analysis?
SP stands for S parameter.
Thanks
Hi,
I'm getting the below error when opening a library in Abstract Generator. The error is related to an information that should be present in the technology file.
The error says : The routing direction for layer M1 has not been specified. Specify the appropriate direction in the routingDirections sub-section of the layerRules section of the technology file.
The error is coming even though the routing directions are defined in the Technology file.
Please let me know a solution to this problem.
Thanks,
Mallikarjun
Hi
I am trying to model a transmission line with the mclin/nclin elelment from the rftline lib. I first created the stackup and then reference the stackup element in the mclin instantiation. My understanding is the tool creates a RLGC matrix for the stackup on a per length basis, and one needs to specify the length of the transmission line in the mclin properties. When the xmission line is say 2 inches long, how should I go about it? The obvious choice of just using one element with length = 2 inches, results in an unexpected change of impedance. Is it better to then break it down into say 0.5 inch elements (length=0.5 inch) and then cascade four of them or should they be broken down into further small elements (say 10 elements -.2 inches long) ? Please advise.
Dear friends,
Is there a tool to simulate the impact of the resistance from the lines in the circuit performance?
I want to obtain the maximum resistance that a line can have without reducing one performance parameter below the expected.
Best regards,
Rafael
Dear All,
I fired a Spectre Simulation in Linux terminal. (spectre filname.scs).
It ran successfully, Is there any way (like some command) by which we can detect the end of the successful or un-successful simulation run ?
Kind Regards,
Hi.
I'm running Quantus RLCK and I noticed that sometimes it creates on or two "nan" valued resistors (either using ladder-network model or not).
This doesn't happen for RC extraction.
The problem is that spectre then halts simulation and throws: " parameter `r': Cannot run the simulation because an unknown parameter `nan' has been specified in expression `-nan'. Correct the expression and rerun the simulation."
Am I doing something wrong? Currenlt, the best I can do is tweak layout to prevent there resistances from being generated
Assura: 4.1_USR6_HF3
Quantus version: 19.1.3-s062
Spectre: 161 through 191, latest USRs
Cheers,
Matan
Dear All,
Can anybody please tell me what is the difference between id and Ids of a MOS operating parameter shown in operating point list of ADE.
Kind Regards.
Dear All,
We can find the transient operating point of MOS device (see as below) with non-extracted or pre-layout netlist.
But, how it can be done when we are using extracted netlist (spf view of the block).
Hi,
I want to include a *.sp in a cdl fie by using .INLCUDE.
But the calibre is showing that there are errors in cdl.
could some body tell me how to include a .sp file in cdl?
Thanks,
Ganesh Doddipatla.
Hello,
What is the appropriate view name to be used in instantiated device component or cell (transistor, resistor, capacitor, inductor, voltage source, and current source)?
Symbol or Spectre view? I have seen some cases where designer use Spectre view for some cells such as transistors, voltage source (vdc, vpwl, and so on) and some cases where they use Symbol view. But for global cell such as gnd they always stick with the symbol view
Does it depend on the model file (bsim or psp) one is using?
Thank you very much indeed.
Hi,
I do have a design (testbench+blocks) and performed MC simulations.
Doing the same simulation again will result with same simulation results.
Now I had to rename the design (testbench+blocks), so I simply copied all cells to a new name.
Nothing internally changed. The config-view was adopted to the new names and the maestro view as well.
But performing the same MC simulation shows different results.
Is this expected ?
Will the rename of a design cause a different seed for the MC simulation and thus results in different simulation results ?
Hello,
I am trying very simple parametric simulation, that is plotting the NMOS I-V characteristics. The simple procedure to do in ADEL is by sweeping the value of VDS from example from 0 to 3.3 in steps of 10m and adding the VGS in the parametric tools from ADEL.
I tried to make this simulation an ADEXL, by creating two variables as VDS and VGS that corresponds to the voltage sources at source and gate respectively. Then in the global variable pan, I defined the same range for VDS and VGS used before in ADEL, I made my test to run only the DC operating point. Now the number of corners are shown 1992, Therefore, this simulation will take a lot of time as compared to the simple setup with ADEL, to make it similar to the ADEL setup I have to sweep the VDS value from the setting of the DC test of the ADE and exclude it from the global variation.
Is there other better option to run the parametric in ADEXL ?,
By the way in my case I cant use the Group as Parametric set as they have different sweep number of steps
Thank you
Regards
Does anyone know if an export license is required if you tape out a high speed ADC chip using TSMC? The ADC chip, if in production, would be export controlled by the US government. But is a license required even at the tapeout stage?
I am currently doing a simulation using an ideal switch from the analoglib with an open resistance of 1Tohm and closed resistance of 1ohm. Also there is a supply (vpulse) given to the switch to define the on time and off time.
Rise time: 1ns, Fall time: 1ns, pulse width: 166ns, period: 10us
I want to convert it to a CMOS transistor based switch. I know that the transistor should be operated in linear region to behave as a switch. That means Uds < Ugs-Ut
But what other factors should I need to consider to exactly replicate the behavour given by the ideal switch (of course it will no longer be an ideal switch when it is implemented using transistor)
How about the width and length of the transsitor used (if it is an NMOS or PMOS based transistor).
How should I come up with how much Ugs I need to supply?
As topic