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Plot analog bus with non-overlayed traces in ViVa

January 8, 2020, 7:09 am
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Hi,

I do have an analog bus "vout<31:0>" and a output expression "VT("/vout<31:0>")", and I want to plot the transient signals.

In ViVa it plots all signals on top of each other (overlayed).

But I want to see each signal in a seperate trace (e.g. like in a logic analyzer).

The only way I found is to have an extra output expression for each signal, e.g. VT("/vout<0>") VT("/vout<1>") VT("/vout<2>") and so on.

But I stronlgy belief (hope) that there is a better way to plot a analog bus transient signal.

Having 16,32 or 64 bit busses and each signal its own output equation would be really annoying.

Please tell me how to plot the analog bus signals each in a seperate trace -  pleeease ;-)

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Graph symbols

January 8, 2020, 11:02 am
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When you get a graph from ADE L in virtuoso, when you right-click and add a symbol to the graph (x,o,+..) is it possible to increase the size of the graph symbol? As I am trying to make them clear in an IEEE paper. Or is there a different way to save the image for IEEE? saving the data to MATLAB or EXCEL cannot be done as I do not have permission from my Uni to access the folder they get saved in and export the data.

Regards,

Qusai

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Resistive-capacitive OTA bandpass filter for low frequency signal acquisition

January 8, 2020, 9:33 pm
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How should I give the  DC average value(VCM) to the input to a fully differential OTA when I am using it in a loop where capacitive input is needed? My signal is a sinusoidal signal with frequency 100hz, and amplitude of the sinwave 10mV peak to peak. VCM=600mV.Kindly help me in this regard.

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how to calculate avg power

January 9, 2020, 12:38 am
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I need to calculate average power in transient analysis using cadence tool, but in tran option i am not getting pwr signal. what is the problem behind that??

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To get the PM and GM from stb analysis for a parameter sweep

January 9, 2020, 3:18 am
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I have a basic opamp with input capacitance (Cin), feedback capacitance (Cf) and  feedback resistance (Rf). Initially I did a stability analysis (stb) with fixed values for all the design variables mentioned. I swept the frequency in a range and got the Phase margin (PM), Gain margin (GM) for the analysis. 

Now I want to sweep the Rf for a range and analyse the stability of the system. For this I have to use a specific frequency (eg. 100MHz) and select the range of Rf. The simulation is running ok and I have the plots for the Loop Gain and Phase. The plots are wrt Rf and not wrt Frequency

But, I am not getting the PM and GM for each Rf. This is because the simulation has not been swept based on frequency. 

How can I get the Stability summary for each iterations from the cadence itself?

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What is the latest version of MMSIM release?

January 11, 2020, 8:54 pm
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Transistors Operating Region check in Ocean Script

January 12, 2020, 3:31 am
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Hi,

I am trying to optimize my design using cadence ocean script to print a results on text file and then I am using Matlab for post processing this results and do iterations. The first criteria I have is to check whether the operating region of Transistor is in saturation or not "if(Region==2)". For 1-dimensional sweep I used to do it by writing "save MP:all" in text file and adding the path in stimulusFile and using using getData("MP:region" ?result "dc") to get transistor operating region.This method works very well in 1-dimensional sweep, however, I tried to use the same way for 2-dimensional sweep and it was not helpful. Does anybody know a way of checking transistors operating region in multi-dimensional sweep?

Thanks,

Ata

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Import/exporting from cadence calculator

January 12, 2020, 3:53 am
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Dear All,

Is there a way to export and import back the equations from cadence calculator or the list of ADE L outputs?

Thanks in advance

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Using one expression value to get another expression in ADE-L

January 13, 2020, 12:54 pm
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Hi,

I have a simple opamp integrator, with input and feedback capacitance (Cin and Cf). I have 2 expressions fot getting settling error voltage at output net and input net.

Settling error(Vin)  - value(VT("/net02") 1.66e-07)

Settling error(Vo) - value(VT("/net3") 1.66e-07)

Now I want to get another expression to find the total charge (Qerror) from each expressions. For that I am using the name of used expressions (Settling error(Vin) and Settling error(Vo)) and multiplying it by the design variables Cf and Cin (VAR("Cin") and VAR("Cf")) . New expression is like this below.

Qerror - (Settling error(Vin) *VAR("Cin") ) + (Settling error(Vo) *VAR("Cf"))

I am not getting any value printed in the expression Qerror

Is there any error that I am doing? Or is it not work in the ADE-L, by just using the signal name?

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Force minimum 2 Vias whenever creating Via in Layout View

January 14, 2020, 3:22 am
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Dear all,

I would like to ask is there any way to force minimum 2 Vias when creating Via in Layout View? In setting cdsenv or SKILL script...

There are some scenarios like: creating bus, creating single via, creating auto via...

Thank you very much.

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Using calcVal() function in ADE Explorer is possible?

January 14, 2020, 5:50 am
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Hi all.

I would like to know if calVal() function is supported in ADE Explorer and if yes, how it can be possible?

Due ADE Explorer has an unique test bench, I have doubt of it.

Thanks

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Ocean: exporting internal circuit signals taking more than 1h

January 15, 2020, 2:42 am
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The following working code saves the voltage of all signals from a circuit in a text file:

I0.U94.net0158 0.999999
ADDR_OUT\<0\> -3.61176e-07
ADDR_OUT\<1\> -3.68596e-07
ADDR_OUT\<2\> -0.000613136

The problem is that this script saves a lot of junk like the following (with the .gi internal transistor signals):


I0.U1_RES_reg_2_.GNI 3.04658e-07
I0.U1_RES_reg_2_.MN1.gi 1.00009
I0.U1_RES_reg_2_.net019 0.999994 

In fact, from ~80k lines, more than 55k lines are with "junk" signals.

Question 1) Is there a way to avoid these ".gi" signals from transistor nodes?

Question 2) It's taking more than 1h to export these ~80k signals after the simulation. Is this normal?

Ocean script:

paths_file_folder = ".../simulator_spectre/"
electrical_simulation_path = .../simulations/"
cell_name = "cell_name"
modelFile_path = '(".../corners.scs" "")
path_psf = strcat(electrical_simulation_path cell_name "/spectre/schematic")
path_netlist = strcat(electrical_simulation_path cell_name "/spectre/schematic/netlist/netlist")
time_hit = 1.8e-08
outputstart_electrical_sim = "1e-08"
stop_electrical_sim = "3e-08"
temperature = 25
vdd_core = 1.0
results_wvspt_folder = ".../waveform/"

simulator( 'spectre )
design( path_netlist )
resultsDir( path_psf )
modelFile( modelFile_path )
analysis('tran ?outputstart outputstart_electrical_sim ?stop stop_electrical_sim ?skipdc "yes")

envOption(
    'cmd64bit  t
    'analysisOrder  list("tran")
)
option( 'dochecklimit "no"
)
option( ?categ 'turboOpts
    'apsplus  t
    'uniMode  "XPS MS"
)

temp( temperature )

saveOption( ?simOutputFormat "psf" )
saveOption( 'currents "none" )
saveOption( 'save "selected")
run()

;Open results from psf
openResults(path_psf)

;Select transient results. Only voltage in this case
all_signals_v = outputs(?result "tran" ?resultsDir path_psf)

;Save operations in the specified file
symmaryFile=outfile(strcat(results_wvspt_folder "all_signals_voltages") "w")

foreach(cell_name all_signals_v
  cell_voltage=value(v(cell_name ?result "tran") time_hit)
  when(cell_voltage
    fprintf(symmaryFile "%s %g \n" cell_name cell_voltage)
  )
)
close(symmaryFile)
ocnCloseSession()
exit()

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Two part functional symbol in Virtuoso

January 15, 2020, 6:49 am
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Hi,

Does Virtuoso have method to support two part symbols? An example would be a relay with a switch and control symbol that is separated but bound to one functional model. This is supported in Allegro PCB designer.

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VHDL-AMS delayed attribute

January 15, 2020, 11:47 am
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Dear all,

I am currently trying to model a simple delay in VHDL-AMS.

entity DELAY is
  port(
    terminal vin : electrical;
    terminal vout : electrical
  );
end DELAY;
architecture behavioral of DELAY is
  quantity vo across iout through vout to ground;
  quantity vi across iin through vin to ground;
begin
  vi == 1.0E12 * iin;
  vo == vi'delayed(1.0E-9);
end behavioral;

However, when I try to simulate that, the input signal is not only delayed but has also a slewrate added. This is shown in the image below (green is vin and red is vout). Does anyone know where this slewrate comes from and how this can be avoided?

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Simulation output results showing different names for the Expression used to calculate

January 18, 2020, 8:30 am
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Hi,

I have some expressions (fig1) that calculates some results. I am running a parametric simulation for a parameter Ron. 

In the plots after the simulation, The name labels for each expression looks different (see fig2). 

Settlinerror(Vin) is shown as error, Q1 is shown as Qerror, Qerror is shown as Q

Why this is the case? Any one have experienced the same situation?

Thanks in advance

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How we can use the single VCVS file containing N waveforms for generating the N voltage waveform sources in ADE-XL ?

January 19, 2020, 4:33 am
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Dear All,

I thought to create a new thread for this post instead of adding to an old but related thread.

We can save N voltage waveforms in a vcvs file by using the thread community.cadence.com/.../1285946

But, how we can use the single VCVS file for generating the N voltage waveforms  in ADE-XL ?

Kind Regards

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Define libraries as read-only

January 19, 2020, 11:37 pm
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Hi,

is there a way in cds.lib to define libraries as "read-only" ?

I do have libs defined in cds.lib from another project, which I want to have read-only.

I do not want to set permissions via the Linux system, because there is a revision control system in between.

Instead I am looking for a way to write-lock (read-only) libs with Cadence settings

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Pole Zero location from stb Analysis

January 20, 2020, 12:49 pm
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Hi,

I am running a Stability analysis ('stb').

Can I see the exact pole zero location from this analysis without doing the 'pz' analysis?

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mosfet model spice/pspice

January 20, 2020, 2:46 pm
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I am simulating a discrete mos device in Spectre.

If I treat it as a spice model the drain-source current is much too low (mA vs amps expected). If I treat it as a pspice model it is good. The model is not supposed to Pspice specific and works OK in other simulators.

Any ideas what might be going on?

.MODEL PMOS PMOS LEVEL = 3 U0 = 400 VMAX = 1E+006 ETA = 0.001
+ TOX = 6E-008 NSUB = 1E+016 KP = 26.45 KAPPA = 19.32 VTO = -0.6929

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Building up array of instances

January 21, 2020, 4:29 am
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Hi,

I wanted to build up an ADC array with different inputs and output in schematic editor. Is there a way to do this efficiently instead of copying, for example, 64 times the instance?  One could use the following instance<64:0>, but then the inputs qnd outputs will be connected to the same bus. So this is not the right method.

Any ideas?

Thanks!

Kind regards,

Nicolas

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