Quantcast
Channel: Cadence Custom IC Design Forum
Viewing all 4891 articles
Browse latest View live
↧

X-View checker for full design hierarchy for applied sigTypes in all instances for schematics and symbols

December 18, 2019, 1:30 am
$
0
0

Hello,

Do you know if there is a full hierarchy x-checker available for sigTypes for Virtuoso, which checks schematics vs symbols throughout the hierachy ?

Background/use-case:

When running SV-netlister in the "logical" mode, no netlisting of power/gnd pins is desired. The netlister is sensitive to all sigTypes on schematics and symbols.

In case of a mismatch between symbol and schematic (symbol-terminal "power", but schematic-terminal/net "signal") - even in the hierarchical check & save the mismatch is not flagged. Running logical netsliter here generates a netlist which i.e. has constants assigned to pins. Such a netlist is consisdered as not correct.

In order to avoid it, one needs to fix the mismatches in handcrafted OA. 

In case you have such a checker (accepting lib-cell-schematic) as a starting hierarchy and checking all hierarchies/instances incl. schematics and symbols, can you point me to it ? Or is there any other way by running check&save (Virtuoso IC 617/IC18).

Thanks.

↧
Search

CDF parameter of View - Default Options

December 18, 2019, 2:29 am
$
0
0

Hello,

I am sure this has come up before but couldn't find it on the forums.

The query is relating to the properties of a VerilogA block. When the block is placed in a schematic and the properties are viewed (using Q) the default “CDF parameter of View” comes up as “Use Tools Filter” which does not show the parameters in the Verilog code (see Fig.1) . It is only after clicking on the view “veriloga” that the parameters can be seen (Fig.2).

Only an inconvenience but I was wondering if there is a way the CDF Parameter of view can be set such that it searches for "veriloga" rather than the current default which is "Use Tools Filter"?

Many thanks, Chris.

 Fig1

Fig2

↧
↧

ICADVM18.1 - using Layout L instead of XL

December 18, 2019, 5:56 am
$
0
0

Hi everyone!

We are encountering a problem because we changed from virtuoso of ICADV12.3 to virtuoso ICADVM18.1.

With ICADV12 we used Layout L. Actually we have the license for GXL but as far as I remember there popped up a question if we want to use Layout L with the GXL license and it worked fine

But after we changed to ICADVM18.1 we only can use Layout XL. I think maybe there is a entry in the .cdsenv file we have to change or delete but I don't know which one.

Any ideas? Thank you for your help in advance.

Best regards
René Hartmann

↧

dspf_include accept spectre syntax?

December 18, 2019, 6:38 am
$
0
0

Looking for a way to use dspf_include to accept spectre syntax (.scs file). Also, where is dspf_include documented?

↧

how to create own via in cadence software

December 19, 2019, 2:31 am
$
0
0

hello sir, is there any method to create own via in cadence (IC 6.15)? I know in the cadence there are custom vias that are available to make the layout design.
2).when I draw my layout design through custom via there is a cross sign above the via. what are the mistakes done by me?

↧
↧

How to flatten a hierarchical design?

December 20, 2019, 12:24 pm
$
0
0

Hi,

I have a hierarchical capture schematic that I need to convert into a flat design and was wondering what are my options to do this how do I go about with this process? 

Any help would be really appreciated with this.

Thanks.

↧

extract min and max over corners for every variable step

December 23, 2019, 1:19 am
$
0
0

Hi Everyone, hi Andrew,

With ADE-XL I would like to run a simulation over multiple variables values + over multiple corners.
For instance in global variables:
VAR1 = from/step/to 1/0.1/10
VAR2 = from/step/to 5/0.2/20
...
+each one over the corners: C1,C2,C3,...

I would like to automatically extract the min and max values over all corners, for each variable step,
and after that automatically plot these min and max values for each variable step. The bonus would be to extract the min and max values and use them to chain other simulations.
On the whole, I would like to make an extract among all corners, as if a multiple corner simulation (for each variable step) were a single simulation.

Could you please explain to me how to do?

Thanks a lot in advance!

↧

layout extraction avoid a specific area

December 23, 2019, 4:14 am
$
0
0

Hi, I am using virtuoso with a foundry CMOS process.
I have finished a layout and passed the LVS by Calibre.
In the PEX, would we have any way to avoid the parasitic extraction on a specific layout area?

Many thanks for the help.

↧
Search

Virtuosity: Looking Back at Virtuoso ADE Product Suite and Virtuoso Visualization and Analysis in 2019

December 24, 2019, 2:03 am
$
0
0

A little present for the holiday season - if you're not already subscribed to the Custom IC Blog series, you might want to take a look at this summary of the Virtuosity and Virtuoso Video Diary series covering new features that came along in Virtuoso ADE and ViVA this year:

Virtuosity: Looking Back at Virtuoso ADE Product Suite and Virtuoso Visualization and Analysis in 2019

It's worth subscribing - that way you get notified when there's new content in the blog series (you just need to provide your email address in the subscription box on the left side of the blog).

Best wishes for whichever holidays you celebrate in your part of the world, and a Happy New Year!

Andrew

↧
↧

How to reduce parasitics from layout

December 25, 2019, 2:37 am
$
0
0

How to reduce parasitics from layout? When i simulate pre-layout and post-layout form of my design there is vast variation in delay and power when i measure. how can I improve my layout design?

↧

technology file manager

December 29, 2019, 11:29 pm
$
0
0

Hi all,

I am getting an issue when opening technology file manager.

The error is 

techManagerOpenTechToolBox()
*Error* eval: unbound variable - ciwvHelpMenu
ERROR

I am using ICADV12.3-64b.

please help me.

Thanks,

Ganesh Doddipatla.

↧

Parameters of a FINFET

December 30, 2019, 10:11 pm
$
0
0

Hi all,

I am new learner of Cadence. While I was performing simulations using FINFET as a device, I found out the voltage across the device using two methods :-

1. By taking node voltages difference

2. Printing the dc operating points of the device and looking at Vds.

These two are not matching. However its matching with one another parameter written as Vdet. I just want to know what all these voltage parameters represent.

Vdet, Vds, Vdssat, Vdst, Ves, Vest, Vfb, Vgd, Vgdt, Vget, Vgs, Vgst, Vgt and Vth.

↧

Launching ADE L failed

December 31, 2019, 1:34 am
$
0
0

Hi, I am using IC617 to integrate simulator with Virtuoso. 

I have following warnings and error happens when I am trying to launch ADE L from Schematic Editor window.

*Warning* hiCreatePulldownMenu: The menu must contain at least 1 entry

*Error* putprop: first arg must be either symbol, list, defstruct or user type - nil

*WARNING* (DEBASE-102079): A SKILL error occured in function _sevDataTrigger

*WARNING* (DEBASE-102084): Data trigger for viewType adestate failed

Those errors happened during doing the CDB2OA conversion.

Could someone help me to solve those problems? Thank you very much!

There is another problem happens when I am trying to run the state tran. it is failed to open the state Tran becaue it uses the spetreVerilog simulator which is not supported by the current version of Virtuoso. Can anyone help me to solve this problem as well?

↧
↧

[Spectre] multiple dynamic parameters ?

December 31, 2019, 2:09 am
$
0
0

Hi Andrew,

We are running under IC6.1.7-64b.500b.14, ADE-XL.
I have a very accurate transient simulation to perform (with less than 0.1ps accuracy) but I am drowned into simulation noise, even with errpreset=conservative. Unfortunately due to high time constants the circuit I am simulating is quite long to stabilize to its steady-state and it would be cumbersome to run a long simulation with ultra-accurate settings; so I would need to (FOR INSTANCE):
- firstly run a pre-transient phase with relaxed settings, such as for instance errpreset=liberal + maxstep=20ns, during let's say 500ns
- after 500ns dynamically change errpreset to conservative AND maxstep=0.1ps for let's say 100ns.

My problem is I do not know how to change multiple dynamaic parameters errpreset+maxstep (weirdly if I remember well I could do that in the past, but not anymore with this Cadence version...), so I have to choose either errpreset or maxstep, but not both at the same time; unfortunally it is not accurate enough for me.

Andrew proposed this workaournd in the Cadence forum here:
community.cadence.com/.../changing-a-group-of-parameters-using-dynamic-parameter-option-available-in-tran
...But, it does not work for me.
Here is what I do (following what Andrew suggests):
- create a .scs file with the exact following syntax:
myset paramset {
time errpreset maxstep
0 liberal 20e-9
500n conservative 0.1e-12
}

- import it in Model Library Setup


- in the Options button on the tran form, >Misc tab. >additionalParams field > paramset=myset

...but I get the following error:
Error found by spectre during hierarchy flattening.
ERROR (SPECTRE-16124): `myset' parameter set was not defined.

Could you please show me the way to change multiple dynamic parameters in my simulation?

Thanks a lot in advance for your help.

↧

making ruler visible from higher hierarchy

January 1, 2020, 11:13 pm
$
0
0

hi guys,

say i mark something with ruler on cell X which is a sub block of cell Y..

i can see the ruler exist in cell X but when i open cell Y i did not see the ruler that was supposed to be in cell X that instantiate in cell Y.\how do i make this possible?

↧
Search

How to create an output expression for given expression using aged and fresh results

January 2, 2020, 8:19 am
$
0
0

Dear Support,

I am running Aging simulation using ADE Assembler and want to create an expression, which represents difference of 10yr and stress or fresh results. I am interested in difference between aged and fresh results for all my output expressions. How can I easily have results table wit those differences. 

Any hints how I can achieve that?

↧

How to sweep multiple params and save the specific param selected from the circuit?

January 3, 2020, 1:54 am
$
0
0

first of all,  i am fresh here. and i am happy to be here.

recently, i am learning how to use ocn. and i met a question troubled me a lot.

simulator('spectre)  //  design(".../netlist")  //  resultDir(".../schematic")  //  modelfile('(".../saveop.scs" "") '(".../toplevel.scs" "top_tt"))

analysis('dc ?saveOppoint t ?dev "/V2" ?param "dc" ?start "0.3" ?stop "1.1" ?lin "200")

envOption('analysisOrder list("dc") )

temp(27)

run()

selectResult('dc)

ocnPrint(?output ".../xx.dat" ?numberNotation 'scientific getData("M0:gm"),....)

this is the code i am use to get param from circuit.

however, i have to sweep multiple params in circuit, and save the params from circuit as mentioned above.

i've tried "foreach, while" synax, and  failed. and i also read the ocnref together with ocn sample script in dfii. 

unfortunately, i could not figure out how~~~

the param sweeping code i attached below:

simulator('spectre)  //  design(".../netlist")  //  resultDir(".../schematic")  //  modelfile('(".../saveop.scs" "") '(".../toplevel.scs" "top_tt"))

analysis('dc ?saveOppoint t )

desVar ("a" 650m)

desVar("b" 300m)

envOption('analysisOrder list("dc") )

temp(27)

paramAnalysis("a" ?values '(0.6 0.62 0.64)

paramAnalysis("b" ?values '(0.3 0.35)))

paramRun()

hope someone could help me~~thanks a lot!!!

↧
↧

Stability factor of differential LNA

January 5, 2020, 11:36 am
$
0
0

Currently designing a differential LNA schematics in virtuoso, my issue is at the output I am using a VCVS. while trying to plot "Kf (stability factor)" it gives no plot, since S12 is zero while using a VCVS making "Kf" infinite. Is there any other way to check unconditional stability? or is there a way to plot "Kf" with a VCVS?

Regards

↧

How to get smooth and accurate output waveform without increasing simulation time

January 6, 2020, 1:58 am
$
0
0

Dear All,

I was simulating a divider (by-2) extracted circuit @ 17 GHz input frequency using transient analysis.

My simulation option was as below:-

simulatorOptions options psfversion="1.1.0" reltol=1e-3 vabstol=1e-6 \
iabstol=1e-12 temp=80 tnom=27 gmin=1e-12 rforce=1 vthmod=vthcc \
ivthn=300e-9 ivthp=70e-9 ivthw=0 ivthl=0 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
dochecklimit=yes checklimitdest=psf
tranCheckLimit checklimit checkallasserts=yes severity=none
tran tran stop=60n errpreset=moderate write="spectre.ic" \
writefinal="spectre.fc" annotate=status maxiters=5

But with the above option, I am getting the output waveform @8.5 GHz as below:-

The waveform is not smooth and many points are missing at the crucial regions. Is there any way we can smoothen the waveform without increasing simulation time significantly.

↧

How to verify LEF vs GDS

January 6, 2020, 8:06 am
$
0
0

Dear forum,

I would like to know how I should verify LEF vs GDS to make sure LEF is really synced with the GDS? What Cadence tools do I need to use?

Is there any recommended flow for this?

Thanks,

Norayr Amirkhanyan

↧
Viewing all 4891 articles
Browse latest View live
Search
<script src="https://jsc.adskeeper.com/r/s/rssing.com.1596347.js" async> </script>