Hi,
I am using ADE-XL and am doing DFTs. I would like to know if I can get a smoothed DFT by for instance making a moving average with a couple of given points (let's say 10) ? as I would need to overlay it to an ideal AC Noise density.
I would like to get the smoothed dft accessible in my ADEXL Results..
Thanks a lot in advance and best regards.
Hi,
I have ADE output format set to fsdb, and planned to read waveform from spectre transient simulation from a waveform viewing tool.
The issue is that I waveform doesn't show while simulation is on-going, evidenced by the fact that fsdb file size doesn't grow, spectre.out file does grow. don't know whether there's be an update from spectre.out to fsdb when the simulation finishes. (will update later). but expect fsdb file refreshed during the simulation to see wavefrom instantaneously.
thanks,
Kevin
Hi everybody,
I just stumbled upon a case where the netlister generated subcircuit names as `subckt libraryname_cellname_cellviewname port_list` instead of the usual `subckt cellname port_list` in the input.scs. How can this be enabled or disabled?
It made the simulation with dspf file problematic due to the different subcircuit naming. I overcome the issue by simply rebuilding the ADE's state. I am just curious what could have caused it.
Thanks,
Zoltan
The used Cadence version is ICADV 12.30.721.
I face annoyingly often the problem that ADE does not plot any results, while CIW reports the error "The wsReloadCommand command generated an exception vector::_M_range_check.". The problem is circumvented by closing and reopening ADE after which the waveforms are plotted.
I have not found this error message in the knowledgebase or in the forum, so probably it is related somehow to my setup. I would like to avoid closing and reopening the ADE if there is any other way. I would be glad for any help or advice about the background of this error. I suspect that an invalid vector index is used, but I am clueless about what specific setting could invoke such an error in my side.
Current tool versions: MMSIM: 19.10.063 & ICADV: 12.30.721.
Hi everyone,
I'm simulating a basic CMOS inverter driven by an ideal squarewave at frequency say 1GHz. Inverter output is a squarewave too.
With a PSS I can see its spectrum and it's of course made of odd harmonics (1GHz, 3GHz etc.. + DC tone).Then I put a PAC=1 signal at the inverter input with frequency range say 100k - 0.5G (the Nyquist frequency of the PSS) with 10 sidebands. At the output I was expecting to see the input bandwidth "redistributed" over the output odd harmonics while around the even ones there would be no signal at all, instead I see the opposite: high gain on even harmonics and no gain around odd harmonics.
Am I misinterpreting the behavior of a PAC simulation? What am I missing?
Thank you in advance
N
Dear Sir,
This to enquire about the procedure to measure the noise spectral density of an amplifier at the output in Virtuoso ADE.
Regards,
Subhajit
Hello,
I am characterizing a BSIM4 MODEL (V4.5). In my variable mapping, I have different dc parameters to be mapped and one of them is self_gain with the unit of rall.
When I run the code, I get an error that says that Reference to non-existent field 'rall'.
My Cadence virtuoso version is: IC 6.1.8-64b.500.9 and my spectre version is 19.1.0.237.isr3
Perhaps there might be a change of unit that I am not aware of.
Thanks for your help.
I'm working from home doing IC layout, so there's a lot of random, complex graphics on my monitors at any given time. I have also heavily edited my display.drf file to give me all the colors I like. I'm finding that I'll do something innocent like bring up a form that needs filling out or initiate a copy command when all of a sudden my layout, or maybe various layers in it, will start flashing between colors. The thing is that the update rate of the flashing is hellishly slow - it's like a curtain slowly and repeatedly lowering as it cycles through the colors and everything slows to a crawl while I wait for the command take effect or the form to become responsive. It's killing my productivity. I have a high bandwidth connection so I really don't think that's the issue. The other thing is that I'll go through periods of up to say 20 minutes where this isn't an issue and then all of a sudden it starts up. Quitting virtuoso or disconnecting from work and reconnecting kind of helps, but it's very spotty. Any idea what's happening here? In case it matters, I'm using nx by NoMachine to connect into work. I did try reaching out to NoMachine support, but as expected they're pointing the finger at Cadence.
LIB-1008 LIB-500 LIB-501 LIB-711 LIB-8 LIB-800 LIB-906 LIB-907 LIB-933 LIB-940 LIB-942 943 966
search in cdnshelp, no result.
Dear All,
I have to export the logic cell counts, types, their co-ordinates with different layer into a text file from the gds file. Can you please suggest how to start?
I have a design that comprises an array of cells that each contain an isolated stack of VDD! and VSS! vias. The cells are made such that they already do correctly hook themselves up to VDD! and VSS! busses at the top met-6 level, although no such supply bussing exist below met-6 (if you don't include the substrate and well contacts at the bottom of the stacks). Any transistors needing supply connections have routes making their way to any one of those via stacks.
I'd like to do the equivalent of a feature routinely found in PCB layout software i.e. pouring a plane, whereby I draw e.g. a VDD! a rectangle around (or even within) the array on a particular layer and it automatically connects to all VDD! nets within the rectangle but carves out the appropriate clearances to everything else. I want to do this to both reduce the parasitic supply resistance and to also shield many of the sensitive nodes at the lower levels from each other. Is this possible in Virtuoso?
Is it possible to control temperature as a dynamic parameter not through `paramset` or other dynamic parameter related arguments to `tran` but via Verilog-A? The reason I'm asking is I have an setup where I have a Verilog-A module that is "in charge" of a simulation. It sets some voltages, monitors for certain conditions, and then once certain conditions are met it changes some voltages and continues. It seems faster than running individual simulations with different setups in this case. I'd like to be able to do the same with temperature but it isn't clear that this is possible. I'm guessing if I use dynamic parameters with fixed times for the change that I'd be better off just running individual sims that step temperature and combining results.
Thanks
-Dan
I had an ADE-L state, what I would like to move into ADE-XL to do corner simulations. My problem is that the PSS's sweep can not be set in ADE-XL. My PSS has some tstab, and I would like to avoid redoing the initial transients. Also this sweep is done only for PSS and not for other analyses. The error message after clicking OK on the form is "Periodic Steady State - "Variable Name" : String does not represent a design variable" in a pop-up window. It is not a typo in the design name, since I select from the GUI list.
Is there any way to use this PSS sweep or I have to sweep the parameter globally?
Thanks,
Zoltan
Hi,
I am developing library file for the transistor model and .sp file to run the file and would like to import this into Virtuoso so that I can work on circuit level. Please help me importing SPICE into Virtuoso. Any help would be appreciated.
Hi all,
I am having a strange problem in designing my VCO.
The problem is:
When I use this kind of biasing and sweep my ideal capacitor to change the frequency, freq varies but VCO output swing changes as well !!
The amplitude variation is low if I dont use that biasing and directing connect GateP to DrainN.
I dont understand what is the issue.
And also I dont want to want full swing for this VCO since if I have full swing the Vgd max will be high
I want to have swing of 1v pp so:
VD swing : (0.9 --> 1.9)
VG swing : (0.2 --> 1.2)
With this setup I prevent transistors entering triode region.
Thank you for your valuable time and effort.
Hello,
I am making a hierarchical schematic, where at the lowest layer I have an inverter, with the multiplier set to pPar("M") so I can scale the gm of the inverter. From 6 of these inverters, I made a differential inverter cell, where in the property editor I have set M=pPar("multi"), just to differentiate the names in the error messages. Then with these inverters I made test benches where I just set these parameters to a constant.
The inverter testbench works like a charm, no problem, but I can't get the differential inverter test bench to work at all. First I am getting the following error:
Exporting a waveform into a vcsv file returns the error:
The wsSaveTraceCommand command generated an exception basic_string::_S_construct null not valid.
Only the first row of the vcsv file is created (";Version, 1, 0"). This was the first time I've exported waveforms generated with Assembler. I had no issue before with the combination of ADE L, Parametric sweep and ViVA XL. My project uses ICADV 12.3. I have not found any related forum entry or documentation. How could I export the waveforms in vcsv? Exporting the values into a table and then exporting into a csv works, but my post-processing script was written for vcsv format.
Hi all,
I am using ADE assembler.
I ran transient simulation and swept the input frequency (Fin) of the circuit. And I use Spectrum Measurement to return a value of the fundamental tone magnitude (Sig_fund) for each sweep point.
Previously, I use "plot across design points" to plot both "Fin" and "Sig_fund", and then use "Y vs Y" to get a waveform of Sig_fund vs Fin. Measure the 1dB Bandwidth with markers.
Can I realized above measurement with an expression in "output setup" ? And how?
I know to set the "Eval type" to "sweep" to process the data across sweep points. But here, it has to return an interpolated value from "Fin" with a criteria "(value(calcVal("Sig_fund" 0) - 1)". I am not sure whether it can be done in ADE assembler.
Thanks and regards,
Yutao
i had encountered error message like this before.
but in liberate, i did not find the entry to input section info.
I'm trying to set up a VHDL-AMS simulation, so I made a new cell, selected the vhdlamstext type, and copied some example from the web. But when I hit the save and compile button, I first got the following NOLSTD error:
https://www.edaboard.com/showthread.php?27832-Simulating-a-VHDL-design-in-ldv5-1
So I added said file to my cds.lib and tried again. But now I'm getting this:
ncvhdl_p: *F,DLUNNE: Can't find STANDARD at /cadappl/ictools/cadence_ic/6.1.7.721/tools/inca/files/STD.
If I go over to the Library Browser, it indeed shows that the library is completely empty. Properties show it has the following files attached.
In the file system I've also found a STD.src folder. Is there a way to recompile the library properly? Supposedly this folder includes precompiled versions, but looks like not really.