Hi,

I need to run a AMS simulation for a testbench that contains VerilogA block,  functional block (Verilog) and Transistor level schematics. From the Figure below you can have a look:

Here, The Input block is modelled in VerilogA, both CTRL and COI are in VerilogD and DelSig is in transistor level. Those views are selected in Config view for AMS simulation. When the AMS simulation is run, it gives an error that says -  ERROR (SPECTRE-16192): No convergence achieved with the minimum time step specified. Last acceptable solution computed at 1.00049 ns.

Can anybody please provide me a solution to solve this error? I am logged and cannot proceed further.

Thanks,

Ashraful

Hi all, 

    Normally when I try to "ls" a design directory I can always see these two files, both of which cannot be opened in a Virtuoso window (or even invisible for data.dm in the library manager). What is the meaning of them and how can I open them? I learned that opening "data.dm" deals with some skill scripts but I am not familiar with it. So could I get some step-to-step guidance to accomplish it? Also the constraint file is always locked by myself and it is annoying that I do not know what is the use of it, or if I can remove it brutally...

   PS: since the whole design environment is under a data synchronisation system, and I was told not to check in "data.dm" when I finish my work. Could I ask why?  Thanks again.

   PPS: my environment: virtuoso 6.1.6 in Linux.

Best regards,

Qilong

I want to modify the resistance of the M1. Any idea how I can do that?

Thanks

Sherif

Hello,

I am trying to install Cadence verification tools in my university but I am totally lost to choose packages.

I will use GF8HP and GF8RF PDK through MOSIS.

So, I installed Assura for DRC and LVS. Assura can make parasitic extraction?

I know there is 2 packages to make extraction too, EXT and PVS.

So, I have to use EXT, ASSURA or PVS to set QRC_HOME?

PVE doesn´t exist any more?

Thanks,

Emmanuel

Dear Friends, I am newbie to hardware design. I have a task to design a burst mode CDR. Typically it should have very fast frequency acquisition time.
In my system, I have a 8 phase clock input. I am sampling my data with this clock. Now I am searching for an algorithm to detect the phase at the mid point of the data (thereby locks in no time). I think I should need a phase selector which is driven by this algorithm.
There are papers in the web related to the topic. But being new to this field some tips and examples would be very helpful.

Hi,

I have a design which I migrated from a 10 metal stack to a 8 metal stack.

It seems that the two "unsupported" metal stacks are still in the layout but I do not find any way to show and remove them. They are not listed as layers (because they do not exist in this PDK).

When I run DRC, I get the error of the unsupported metal layers. After clicking on the DRC error, the regions are highlighted where the metals are (and are supposed to be). But I find no way to mark and remove them.

Thanks!

Hi,

When I want to run simulation in Spectre, I noticed that the instances whose terminals are connected together are being removed. Is there a way to keep them even if their terminals are shorted together?

Thanks,

yayla

Hi,

I am struggling for many hours with the following: The standard cells in my PDK have the views cmos_sch (transistor level), abstract, adms_vhdlams, verilog.

I would like to perform basic functional testing of basic, custom logic but the transient sim takes forever.

My hope is that abstract, adms_vhdlams or verilog could be used as behavioral model, speeding up the sim by multiple orders of magnitude. However, I have no idea what I am even supposed to do.

I tried the following:

1.) Use the HED to change the views of the cells to abstract and verilog and use Spectre, APS or XPS MS.

In all cases, references to the standard cells do NOT appear in the netlist. Subcircuits containing only standard cells become empty. Hence, the result browser does barely contain any signals and the one it contains are zero.
I am not sure if this is supposed to be the case or not.
Maybe the View List or Stop List needs to be modified? (I tried adding "verilog" to both without success)

If I set the views to adms_vhdlams, then I get an error like:

    ERROR (SFE-23): "input.scs" 22: The instance `I0' is referencing an undefined model or subcircuit, `C12T28SOI_LL_IVX4_P0(VHDLAMS_WRAPPER)'. Either include the file containing the definition of `C12T28SOI_LL_IVX4_P0(VHDLAMS_WRAPPER)', or define `C12T28SOI_LL_IVX4_P0(VHDLAMS_WRAPPER)' before running the simulation.

2.) Using AMS. My normal setup uses ic/6.17.701 and spectre/16.10.187; now I additionally load ius/8.20.006. I again use HED to create a new config and use AMS as a template. I select Plugins -> AMS and AMS -> Initialize.

Now weird things start already because I cannot close the HED any more, nor the CIW (I can only kill virtuoso). An attempt to close either just results in:

*Error* eval: unbound variable - _amsaIeConnectRulesInfo

In any case, I can continue by selecting opening the schematic/ADE L with the config and running the sim with AMS. However, then I get the following error in the CIW:

[...]
---------- End of netlist configuration information   ----------
INFO (VLOGNET-80): The library 'playground_ams', cell 'inv2_ams', and view 'config' has been netlisted successfully.

End netlisting Mar 22 00:19:51 2017
INFO (AMS-1243): AMS OSSN netlisting has completed successfully.
To view the modules, choose Simulation->Netlist->Display.
      ...successful.
create cds_globals...
*Error* IE cards generation failed.
      ...unsuccessful.
      
I tried the same with incisive/14.20.003; or even without either; same results.

3.) Use again HED and pick spectreVerilog as template. However, when opening ADE L, I cannot choose spectreVerilog as simulator. I do not know which configuration/package is necessary to make this visible.


Any ideas of either of these questions/problems??

Thank you!

Hi,

I'm new to Verilog-A I am having convergence issues with a device I modeled in Verilog-A. When I have the device simulated in parallel with a time varying voltage source then the simulation seems to work okay. The issues arise when I try to simulate transient behaviour of my device in series with an added resistor and the voltage source in parallel with both the series resistor and Verilog-A device (as seen in image if I added it correctly).

The code for the device is below.

[CODE]
`include "constants.vams"
`include "disciplines.vams"

module test_func(p,n);

    inout p,n;
    electrical p,n;

    //files for reading/writing
    integer mcd, fp;

    real data, v_present, v_step;

    real preisach_density[0:256];// all elements should add up to 1
    real domain_states[0:256];// all elements should be -1 or +1 (depending on polarity)
    real polarization;//polarization (between -Pr and +Pr)
    
    real polarization_prev, polarization_next;
    real time_prev, time_next;

    integer i, j, k;//used in loops

    integer rows, columns;//describes area scanned from applied voltage
    integer rows_total, columns_total;//gives number of rows and columns in the grid ("rows" and "columns" should not exceed these values)
    
    analog begin    

        @(initial_step) begin

            //read data from csv file and transfer it to verilog-A array variable
            //data stored in csv file should be preisach distribution
            //csv file should have the same number of elements as arrays "preisach_density" and "domain_states"
            mcd=$fopen("test6.csv","r");

            while (!$feof(mcd)) begin

                $fscanf(mcd,"%f", preisach_density[i]);
                domain_states[i] = 1;

                i = i+1;
                  end

        //****************** v_step should be changed, should equal resolition of grid spacing
        v_step = 0.1; //arbitrary

        rows_total = 1.6/v_step;//the maximum anticipated applied input voltage divided by the resolution of the grid cells
        columns_total = 1.6/v_step;//the minimum anticipated applied input voltage divided by the resolution of the grid cells

        polarization_prev = 0;

        time_prev = 0;
        time_next = 0;
        
        end

        if (V(p,n) < 0) begin

            rows = V(p,n)/(-v_step);

            for(j = 0; j < columns_total; j=j+1) begin

                for(k=0; k<rows; k=k+1) begin

                    domain_states[k*columns_total + j] = -1;

                end
            end
        end

        if (V(p,n) > 0) begin

            columns = V(p,n)/(v_step);

            //value compared to j should equal number of columns in array
            for (j=0; j<columns * rows_total ; j=j+1) begin

                domain_states[j] = 1;

            end
        end

        polarization = 0;
        for (i=0; i<columns_total*rows_total; i = i+1) begin

            polarization = polarization + preisach_density[i]*domain_states[i];

        end

        
        polarization_prev = polarization_next;
        polarization_next = polarization;
        time_prev = time_next;
        time_next = $abstime;

        I(p,n) <+ (polarization_next - polarization_prev)/(time_next - time_prev);

    end

endmodule
[/CODE]

The error I get is:

Error (SPECTRE-16080): No DC solution found

I also get "Array access out of bounds" errors when the device is simulated in the circuit shown but this does not occur when it's just the device in parallel with the voltage source with no resistor. Does anyone have suggestions for how I can solve these issues?

DC Operating point info for devices using BSIM-IMG model (mainstream model for FDSOI transistors) seems to contain only charge and capacitance information.

BSIM transistor models have traditionally included relative terminal voltages, transconductance, threshold voltage, etc. which are very useful for design. They're included in Operating point parameters for BSIM4, BSIM-CMG and even UTSOI (non-VT based model) models. Wondering if there's a reason they're excluded for BSIM-IMG devices or if they're just not included because the model is used relatively rarely. Does anyone have insights into this? The question is probably too specific - but any insight is much appreciated! :)

Hi Andrew,

I have a very weird problem. I have checked other posts but couldn't figure it out. Hence, I decided to post here.

So I'm simulating a design in spectre simulator (an extracted netlist in spectre format). I have an ocean script and simulation runs without any problem. I want to do some calculations with the results.

However, I cannot seem to access any of the low level nets (although I can see them with outputs() command). 

For instance after typing outputs(), I get:

("/C/N_XC11/XLC/TCONF<128>_XC11/XLC/XBLE<2>/XLUT/XLUT_L1<0>/XI0<0>/MM2<0>_g" "/C/N_XC11/XLC/TCONFB<128>_XC11/XLC/XBLE<2>/XLUT/XLUT_L1<0>/XI0<0>/MM13<0>_g" "/C/N_XC11/XLC/TCONF<130>_XC11/XLC/XBLE<2>/XLUT/XLUT_L1<0>/XI0<0>/MM2<2>_g" "/C/N_XC11/XLC/TCONFB<130>_XC11/XLC/XBLE<2>/XLUT/XLUT_L1<0>/XI0<0>/MM13<2>_g" "/C/N_XC11/XLC/VSS_FIRE<5>_XC11/XLC/XBLE<2>/XLUT/XOTP<2>/XPUF_CELL/MHCI_TR_s" "/C/N_VSS_XCH_DUMMY/X33/XI8/XI203/MM5_s"

)

As seen here, I'm trying to access some low level nets. 

when I try getData("/C/N_VSS_XCH_DUMMY/X33/XI8/XI203/MM5_s"), it returns nil. Also tried to access nets that were part of an array (<>) by using "\", that didn't work either.

I tried getData("C.N_VSS_XCH_DUMMY.X33.XI8.XI203.MM5_s"), again getting nil. For some reason I cannot access any of the available nets. I checked runObjFile, directories (netlist>map, amap, psf etc.). Everything seems to be ok. I will be glad if you can help me out. 

Any help greatly appreciated. Thanks

Burak

Hi,

This question is based on https://community.cadence.com/cadence_technology_forums/f/38/t/37113 which explains that for AMS, the signal names have to be preceded by the name of my top level module (e.g. "tb_spi.") whereas not for Spectre etc.

Now I face the problem that I have about 10 stimulus files which I use a) for Spectre, AFS and AMS b) for different test benches.

I end up copying each file 7 times, replacing only the "vname" line, e.g.:

vname MOSI

vname tb_spi.MOSI

vname tb_top.MOSI

etc.

Is there an easy way to handle this? E.g. Telling AMS the vname prefix via a command line switch set through ADE L or an additional config file included via ADE L?

In the worst case, I would write a 'sed' script to do auto replacement but I would like to avoid this to avoid inconsistencies ...

Thanks!

I'm interested in being able to *quickly* simulate some device small signal characteristics versus some parameter (design variable, temperature, etc).  A dc sweep with dc operating point enabled in ADE-L (or even just straight up spectre from the command line) only reports dc operating points (like gm, gds, etc) at the start point.  I've enabled saving as much as I can in the Save All area.  A careful inspection of 'spectre -h dc' would seem to imply that indeed you can't save off operating points as part of a dc parameter sweep.

I can do a parametric analysis, but the overhead of spectre starting and loading the netlist each time is pretty awful.

I can use a 'sweep' analysis in spectre and if I'm in ADE-L I can play games with puttting the 'sweep' analysis in a model file that gets included.  But... then when it comes to results, each point shows up as a single analysis and I don't have a clean way to combine them all unless I write some ocean code to dig through each but that seems like a hack.

If I just put together some loops in ocean, it looks like spectre is indeed running in interactive mode (batch would be even slower).   However, I'm seeing something like 2.5 seconds per point with an ocean script which quite frankly stinks for a circuit with 1 transistor.  I should be able to run 1000 points in a few seconds (or less) instead of almost an hour.

It may be that my best choice is a nested set of 'sweep' runs in a command line spectre and then use python to grab out data from the spectre logfile.  Surely there should be a better (faster) way?  Spectre has the underlying horsepower to where this should be a nothing sort of job.  I suppose another alternative is to use python to generate a really big netlist with all of my operating points which may be a few thousand, and just get them all at once in parallel.  

Hi all,

First of all, I am using Virtuoso 6.1.7-64b.

I need to run transient corner sims for an analog circuit, and the first ADEXL run resulted

in a lot of failures due to DCOp calculation failures. I then use the spectre.ic file in one of  

the successful runs to help the failure ones by enter its path in the "readic field inside the

transient options -> Algorithms.(Method A)

When I tried to run a few failure corners after this under ADE-L, SPECTRE finished

the sims successfully. However, when I load the ADE-L with the "readic" field set,  into

ADE-XL and run the corner sims again, the previously test case corners are still failed.

It looks like ADE-XL doesn't pick up the "readic" info.

In addition, I tried method (B) as follows:

I follow the info. in this previous thread to use an alternative way to include initial condition file:

https://support.cadence.com/apex/ArticleAttachmentPortal?id=a1Od0000000ussjEAA&pageName=ArticleContent&sq=0050V000006VsoqQAC_201732620273064

(i) ADEXL does pick up spectre.ic file 
(ii) both standalone ADE-L and ADE-XL both 
read in the spectre.ic file, but they both failed with DC OP convergence issue

However, the same spectre.ic file when read in using method (A) above,
helps SPECTRE finished the sims properly without issues.

So the question now: how to make "readic" in method (A) above
works under ADEXL, or any workarounds?



Thanks,
Kevin. 

Hi,

I am getting following ERROR in ADEXL.  It is a tran run.

But, If I run it in the "test editor" or the "open debug environment" ,  the run completes properly and gives result.

Kindly help me to resolve the issue.

I am using Virtuoso 6.1.6

------------------- ERROR message in CIW --------------------------

*** SPECTRE ASSERTS INFO: Invoking psf2ferret...Failed
Error : psf2ferret failed to convert assert violations psf to sqlite

-------------------------------------------------------------------------------

Thanks

Soman

Hi,

I'm trying to reduce the simulation data for a really large circuit. I'm going to do MC analysis and have to save family plots. I'm already saving specific nets. Also disabled saving all info files by using 

saveOption( ?outputParamInfo nil )
saveOption( ?elementInfo nil )
saveOption( ?modelParamInfo nil )
saveOption( ?infoOptions list(list("modelParameter" "models" "rawfile" "" "" "" nil) list("element" "inst" "rawfile" "" "" "" nil) list("outputParameter" "output" "rawfile" "" "" "" nil) list("designParamVals" "parameters" "rawfile" "" "" "" nil) list("primitives" "primitives" "rawfile" "" "" "" nil) list("subckts" "subckts" "rawfile" "" "" "" nil) list("asserts" "assert" "rawfile" "" "" "" nil) list("extremeinfo" "all" "logfile" "" "yes" "" nil) list("oppoint" "oppoint" "rawfile" "" "" "" nil) list("<Click_To_Add>" "none" "rawfile" "" "" "" nil) ) )

When I checked the simulation directory, finalTimeOP.info file seems to be only .info file that was saved (~400MB). Is there a way not to save this one? I couldn't see this option under save _all tab.

Thanks

Burak

[Please visit the site to access the poll]

Hi,

Would like to know the exact definition of Retaining rise, Retaining rise slew parameters as they seem similar to Cell rise,Rise transition in .lib file.

Can anyone state the exact difference between them and how to measure them.

Thank you.

Hi,

I am trying to run the simple example as depicted in the attached image, taken from Cadence's "Virtuoso Spectre Transient Noise Analysis" document, page 24.
link is support.cadence.com/.../ArticleAttachmentPortal;pageName=ArticleContent&sq=005d0000005nSd1AAE_20173303123103

But, I am not able to implement the resistor (with the user defined parameter kf) as required here!
here is my setup and simulation process:
1>insert instance "res" from analogLib in schematic editor

2>change its "model name" to say "res_mod" and also made a model file (res.scs)

3>then added this model file from ADE->Setup->Model Path. The text put in this model file is:

simulator lang = spectre
model res_mod resistor rsh=1k kf=10e-13

4>set following parameters at "tran" analysis.

I am getting error of following

looks the circuit is not stable, and i searched the forum and found the same topic of following link. but i cannot find the final solution.

https://community.cadence.com/cadence_technology_forums/f/38/p/31559/1340473#1340473

could you help to check this? thanks a lot.