Hello:

I did a new update and hotfix to Virtuoso Custom IC Design Environment version IC6.1.7-64b.500.10 and I am starting to get all kinds of weird errors.

Whenever, I want to create a test in ADE L or XL I get the following errors:

*Error* (Default-reader-method) generic:asiGetField class:list

<<< Stack Trace >>>

(... in unknown ...)

(... in asiHiGetField ...)

(... in asiHiGetFieldVal (analysis t t) ...)

(... in asiGetAnalysisFormFieldVal ...)

asiGetAnalysisFormFieldVal(hiGetCurrentForm() 'dcmatch 'method)

(asiGetAnalysisFormFieldVal(hiGetCurrentForm() 'dcmatch 'method) != "statistics")

if(_asiIsSessionAMS(asiGetSession(hiGetCurrentForm())) t (asiGetAnalysisFormFieldVal(hiGetCurrentForm() 'dcmatch 'method) != "statistics"))

if(_asiIsSessionAMS(asiGetSession(hiGetCurrentForm())) t (asiGetAnalysisFormFieldVal(hiGetCurrentForm() 'dcmatch 'method) != "statistics"))

(... in asiFormFieldObjCB (asiAnalysisForm) ...)

(... in asiFormFieldCB ...)

(... in asiFormOKObjCB (asiAnalysisForm) ...)

asiFormOKObjCB(stdobj@0x26899860)

asiCheshireCat13(formStruct@0x19c69098)

hiFormDone(_asii_spectre8_analysis_form)

...

t

Hello,

I am trying to simulate a Verilog-AMS model of an ideal ADC, together with some Verilog-A and Verilog modules. Versions of the tools I use:

virtuoso : IC6-1-6.64b.500.11

spectre : 13.1.1.292.isr12 64bit

irun(64) : 14.10-s008

Netlist and run mode: AMS Unified Netlister with irun

Output log gives the following simulator parameters:

Important parameter values:
start = 0 s
outputstart = 0 s
stop = 1.89433 us
step = 1.89433 ns
maxstep = 18.9433 ns
ic = all
useprevic = no
skipdc = no
reltol = 100e-06
abstol(V) = 1 uV
abstol(I) = 1 pA
temp = 27 C
tnom = 27 C
tempeffects = all
errpreset = conservative
method = gear2only
lteratio = 10
relref = alllocal
cmin = 0 F
gmin = 1 pS

The Verilog-AMS code for the ADC looks like this:

always @ (posedge dclk) begin
   rin = V(vin) ;
   sample = V(vin) ;
   for (i=`NBITS-1; i>=0; i=i-1) begin
      is_over = (sample > halfref);
      if (is_over) sample = sample - halfref;
      sample = 2.0 * sample;
      dout[i] = is_over;
   end
end

Here, dclk and dout are of logic discipline, and vin is of electrical discipline. It works correctly except for some samples.

Here is a particular sampling instant:

There is a difference of 40 mV between V(vin) and the sampled value rin, which is unacceptable for my application.

I also checked the computed points and observed a cluster of points near the rising clock edge, but the sampled value occurs quite far away from this edge:

The time difference between those two samples is more than 4ps, but I use a timescale precision of 1fs in all my Verilog and Verilog-AMS modules in the netlist, so I have no idea where this error comes from.

Do you have any idea on the cause and solution of this abnormality? Or an advice on how to further debug?

Thanks in advance!

Arda

Hi everybody!

Hope you enjoy the good health!

Now i am designing the Switched capacitor for Pipeline ADC. I want to check the loop stability for that circuit such as PSS + PSTB. I try to follow several document which i search on the internet. however, there are have some problem in my simulation. When i check the loop gain, the result is too different from what i calculate.

Here is the document which i referred: www.lumerink.com/.../HW2_Kehan.pdf

Currently, i am using Ideal Opamp and Ideal switch

Gain : Gm*Rout = 120 dB.

when i check the Open Loop gain by using the PSS+ PAC simulation like below simulation cell. the result is the same. 

 - Simulation cells

- Result : 

- and then i do the PSTB simulation.as you can see. in my circuit, there are have two loop individually (SAMPLING LOOP and AMP LOOP) and the AMP is differential amp. so, i use diffstbprobe to check the stability.

However, when i check the loop gain, the result is too low compare to Open loop gain which i checked by using PAC simulation. The loop gain is about 52 dB. you can see below. 

actually, i am confusing about the method how to check stability of AMP. i have a question. 

It is possible to use diffstbprobe to check the loop gain of switched capacitor? because as we know,  the gain is ratio between OUTPUT and INPUT signal. But the diffstbprobe have only checked OUTPUT signal. 

and There are have anyone know about that please help me!

Thanks & Best Regard

Hi,

I have a complex simulation where we expect flicker noise AND thermal noise to cause problems. So for a useful simulation I need the noisespetrum of 0.3 - 10MHz at least. The interesting timespan for the simulation is around 10us.
So my sim parameters would be Fmax=10M, Fmin=0.3, tstop=3+10us and I only save the last 10us. But for that  I surely get too long run times.

So I tried to break up the sim into two:

1. Simulate only with flicker noise <10kHz up to 2.999s, then save that timepoint  (intention: noisesources build up)
2. Simulate with full noise starting from the timepoint 2.999s and finish sim   (intention: low noisesources are further evaluated and thermal noise is added)
3. As I need statistics I used a bunch of shell scripts to run 100 sims and for each remove the noiseseed parameter (so they are random each time)

Results look quite(1) ok, but is this the way to go?

Better would be to use dynamic parameter, but that's not featured (yet) for multiple transient runs and I think fmax is anyway no parameter...

(1) quite ok means: Fits better to lab than others, but in the 2nd sim all noise collapses to 0V 50ns after start and restart quickly after that.

I am doing basic SNDR simulations on the SNDR of a 10 bit SAR ADC. I noticed that at moderate input sinusoid frequencies, the SNDR starts degrading. To eliminate any errors in my simulation setup, I ran a test simulation with an analogLib vsin source. The sinusoid frequency is 600e3/1024*23 = 13476.5625 Hz (600e3 = ADC sampling frequency, 1024 for FFT, 23 for coherent sampling/getting all ADC codes). I take FFT of the sinusoid output, with different period of the sinusoid. If the sinusoid perid is 1 cycle, the spectrum is as expected a single contribution at ~13476.5625 Hz (reported 13476.56 Hz. The FFT looks good upto time duration of 10 cycles. But as the FFT period is increased, non-fundamental frequency components appear in the plot. For FFT duration of 23 cycles, the fundamental (13476.5625 Hz) is about 580 mV (insted of 1 V), and there are two neighbouring contributions at 300 mV each (12.89062 kHz and 14.0625 kHz). I increased the precision of the FFT start and end times, but that did not improve the FFT.

Is this a spectre/fft precision issue, or some real phenomenon? Any related tips on cohereent sampling of ADC with spectre?

Thanks,

Mohit

Hello,

For the below cds_srr function  call, I am getting error in matlab. could you please suggest if it is a known bug or if there is any workaround available?

Please let me know if you need more details.Thanks

Tool Version:

Matlab version: R2015A

MMSIMHOME=/p/hdk/cad/mmsim/14.10.804
MMSIM=/p/hdk/cad/mmsim/14.10.804
MMSIM_OVERRIDES_VER=14.10.804.0

CODE: struct_n = cds_srr(c.outfile, c.sweep, params_

Error:

Undefined function or variable 'cds_innersrr'.

Error in cds_srr (line 20)
sig = cds_innersrr(dirname, dataset, signame, verbose);

Error in techsweep_spectre (line 58)
struct_n = cds_srr(c.outfile, c.sweep, params_n{1});

My question is similar to the one in the following thread

https://community.cadence.com/cadence_technology_forums/f/38/t/33153

I also read some other posts on jitter and phase noise sim, but still could not get an clear answer.

Below is what I want to know:

I have a very good clk source (say a TCXO). It is very good but still has some specified phase noise, like -140 dBc at 1kHz offset, -150 at 10kHz offset, etc. Now I added a bunch of buffers to this clk input, which will degrade the phase noise, and I want to know how much the phase noise is degraded, or what phase noise I can get at the output of those buffers.

The way I am trying it right now is to use pss+pnoise, and choose noise type=jitter (PM jitter for driven circuit). After simulation is done, I can plot Jee over a certain frequency offset range and then calculate PN using db20(Jee*2*pi*fin). In order to make things simple, I created the following test bench, just a input a source, plus a small load cap.

Now the question comes:

1. What kind of input port should I use? I can use a port and sine wave input, then I can specify the noise in noise/freq pairs. This way, if I use noise type=source, I can plot phase noise after the simulation is done, and the phase noise at vout is the same as I specified in the port. But if I choose noise type=jitter and calculate the phase noise by  db20(Jee*2*pi*fin), I get much worse results, 8 to 20 dB worse, depending on offset frequency. This confuses me.

2. By reading the manuals and application notes, I found the Jee for driven circuits, using noise type=jitter, simulated the jitter of the circuit, assuming an ideal input source, with an ideal zero-crossing. What if my input input source also is not idea, how can I estimate the total phase noise at the output of the circuit.

3. If I want to use a pulse input (square wave), then I can not specify the relative phase noise as dBc/Hz, I can only specify noise power as V2/Hz at different offset. How to translate the dBc/Hz spec that I have for the input clk to the noise power to be used in the input port in the simbench is another thing that confuses me. This is also related to question 1.

4. In short, should I use noise type=jitter or noise type=source for my simulation? What kind of input source should I use and how do I specify the phase noise of the input source?

Many thanks!

Gang

I've recently been spending some time trying to really understand how some power and ground meshes were done in a layout.  I've been using probing in Layout-XL with the Net Probe Hierarchy Level set to 32 because I want to see all the metal and vias on any level.  Unfortunately what I'm seeing is that this is *slow*.  Probably because it is a large and complex layout.  I'm wondering if there is a better way.  I've wondered about writing a custom DRC deck for PVS to try and pull out a single named net using some of the connectivity based rules and then just load back this layout.  Still, I wonder if there is a better/easier way what won't involve me writing PVS code (which I generally prefer to avoid).  If I have to go the DRC route, does anyone have a simple example of pulling out a net from a layout (probably only using metal/vias for connectivity) and writing back to a stream file that I could stream into a single net cell?

As it currently stands, it takes 15-30 seconds to move/zoom, etc with the probes on.

Thanks

-Dan

Hi,

I am trying to import a CDL netlist into virtuoso. I am able to succesfully import the design but it is very hard to read the design. Currently I see that instances which can be generally grouped as a bus are also expanded when I import it. For example suppose I have this in the cdl netlist

X1 A<1> VDD VSS B<1> mux

X2 A<2> VDD VSS B<2> mux

....

X100 A<100> VDD VSS B<100> mux

The import creates a different instance for each of these instances. If instead there was an option to make it a bus based instantiation it would make the schematic so much more readable and compact.t

Is there any option to do this? Either during import or I don't mind having to run a skill after as well.

Please help out here as I have too big a netlist.

Thanks,

Shraddha

Hai,

I am trying to simulate one schematic which includes the variable capacitor (designed using Verilog-A).  While simulation, I am getting some errors which I could not figure out.

Can someone help me?  I am pasting the log file

Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator
Version 15.1.0.385.isr3 32bit -- 22 Feb 2016
Copyright (C) 1989-2016 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence, Virtuoso and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.

User: Newton   Host: Newton.vlsi   HostID: 10AC3F0A   PID: 76922
Memory  available: 674.8651 MB  physical: 3.9027 GB
Linux   : Red Hat Enterprise Linux Client release 6.9 (Santiago)
CPU Type: Intel(R) Xeon(R) CPU E5-1607 v3 @ 3.10GHz
All processors running at 1200.0 MHz
        Socket: Processors
        0:       0,  1,  2,  3
        
System load averages (1min, 5min, 15min) : 19.0 %, 18.0 %, 9.5 %


Simulating `input.scs' on Newton.vlsi at 12:30:29 AM, Sun Apr 9, 2017 (process id: 76922).
Current working directory: /home/Newton/simulation/varcap_test/spectre/schematic/netlist
Command line:
    /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/bin/spectre  \
        input.scs +escchars +log ../psf/spectre.out +inter=mpsc  \
        +mpssession=spectre0_60350_2 -format psfxl -raw ../psf  \
        +lqtimeout 900 -maxw 5 -maxn 5
spectre pid = 76922

Loading /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/cmi/lib/5.0/libinfineon_sh.so ...
Loading /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/cmi/lib/5.0/libphilips_o_sh.so ...
Loading /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/cmi/lib/5.0/libphilips_sh.so ...
Loading /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/cmi/lib/5.0/libsparam_sh.so ...
Loading /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/cmi/lib/5.0/libstmodels_sh.so ...
Reading file:  /home/Newton/simulation/varcap_test/spectre/schematic/netlist/input.scs
Reading file:  /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/spectre/etc/configs/spectre.cfg
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_bjt_v121.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_bjt_v121.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_mimcap_v101.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_mimcap_v101.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_reg18bpw_v123.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_reg18bpw_v123.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_reg33bpw_v123.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_reg33bpw_v123.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_res_v141.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_res_v141.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_res_v141.va
Reading link:  /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/spectre/etc/ahdl/discipline.h
Reading file:  /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/spectre/etc/ahdl/disciplines.vams
Reading link:  /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/spectre/etc/ahdl/constants.h
Reading file:  /home/Newton/cadence_tools/MMSIM/MMSIM151/tools.lnx86/spectre/etc/ahdl/constants.vams
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_lvt18_v113.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_lvt33_v113.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_reg18_v124.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_reg18_v124.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_reg33_v114.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_reg33_v114.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_zvt18_v121.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_zvt18_v121.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_zvt33_v113.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/core_rf_v2d4.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/core_rf_v2d4.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/io_rf_v2d3.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/io_rf_v2d3.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/l_slcr20k_rf_v2d3.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/l_slcr20k_rf_v2d3.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mimcapm_rf_v2d3.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mimcapm_rf_v2d3.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mim.va
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/pad_rf_v2d3.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/pad_rf_v2d3.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/rnhr_rf_v2d4.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/rnhr_rf_v2d4.mdl.scs

Warning from spectre in `rnhr_rf', during circuit read-in.
    WARNING (SFE-2296): "/home/Newton/Documents/UMC180/UMC_18_CMOS/../Models/Spectre/./rnhr_rf_v2d4.mdl.scs" 8: The inline subckt definition `rnhr_rf' does not contain any inline components. The `inline' qualifier will therefore be ignored.

Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/rnnpo_rf_v2d4.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/rnnpo_rf_v2d4.mdl.scs

Warning from spectre in `rnnpo_rf', during circuit read-in.
    WARNING (SFE-2296): "/home/Newton/Documents/UMC180/UMC_18_CMOS/../Models/Spectre/./rnnpo_rf_v2d4.mdl.scs" 8: The inline subckt definition `rnnpo_rf' does not contain any inline components. The `inline' qualifier will therefore be ignored.

Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/rnppo_rf_v2d4.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/rnppo_rf_v2d4.mdl.scs

Warning from spectre in `rnppo_rf', during circuit read-in.
    WARNING (SFE-2296): "/home/Newton/Documents/UMC180/UMC_18_CMOS/../Models/Spectre/./rnppo_rf_v2d4.mdl.scs" 8: The inline subckt definition `rnppo_rf' does not contain any inline components. The `inline' qualifier will therefore be ignored.

Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/vardiop_rf_v2d3.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/vardiop_rf_v2d3.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/varmis_18_rf_v2d3.lib.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/varmis_18_rf_v2d3.mdl.scs
Reading file:  /home/Newton/Documents/UMC180/Models/Spectre/mm180_diode_v113.mdl.scs
Reading file:  /home/Newton/Desktop/work/PhD_work/varcap/veriloga/veriloga.va
Time for NDB Parsing: CPU = 91.986 ms, elapsed = 170.808 ms.
Time accumulated: CPU = 104.983 ms, elapsed = 170.812 ms.
Peak resident memory used = 31.9 Mbytes.


The CPU load for active processors is :
        Spectre  0 (62.5 %)      1 (43.8 %)      2 (43.8 %)      3 (29.4 %)
        Other   
Opening directory input.ahdlSimDB/ (775)
Opening directory input.ahdlSimDB//cbca1efacc0b5f822e93584eeafed5ab.varcap.ahdlcmi/ (775)
Opening directory input.ahdlSimDB//cbca1efacc0b5f822e93584eeafed5ab.varcap.ahdlcmi/Linux/ (775)
Compiling ahdlcmi module library.

Warning from spectre during AHDL read-in.
    WARNING (VACOMP-2397): Compilation failed when using pipe build. Bytecode flow will be used for encrypted VerilogA, and normal file compilation will be used for unencrypted VerilogA.

Compiling ahdlcmi module library.

Error found by spectre during AHDL read-in.
    ERROR (VACOMP-1008): Cannot compile ahdlcmi module library. Check the log file input.ahdlSimDB//cbca1efacc0b5f822e93584eeafed5ab.varcap.ahdlcmi/Linux//..//ahdlcmi.out for details. Contact your Cadence Customer Support representative with the netlist, log files, behavioral model files, and any other information that can help identify the problem.
    ERROR (SFE-91): Error when elaborating the instance varcap. Simulation should be terminated.

Time for Elaboration: CPU = 37.994 ms, elapsed = 1.04592 s.
Time accumulated: CPU = 142.977 ms, elapsed = 1.21686 s.
Peak resident memory used = 38.1 Mbytes.


Aggregate audit (12:30:30 AM, Sun Apr 9, 2017):
Time used: CPU = 144 ms, elapsed = 1.22 s, util. = 11.8%.
Time spent in licensing: elapsed = 31.9 ms.
Peak memory used = 38.1 Mbytes.
Simulation started at: 12:30:29 AM, Sun Apr 9, 2017, ended at: 12:30:30 AM, Sun Apr 9, 2017, with elapsed time (wall clock): 1.22 s.
spectre completes with 2 errors, 4 warnings, and 0 notices.
spectre terminated prematurely due to fatal error.

Hi,

I would like to simulate I/Q crosstalk in my system (and specifically assess whether I can use 50% duty cycle which is known to be problematic for I/Q crosstalk because two branches are used at the same time).

I set up a testbench where I create a signal cos(2pi fc t)sin(2pi fi t) - sin(2pi fc t)*sin(2pi fq t) where fc=1GHz, fi=10MHz and fq=20MHz. Ideally I should see only 10 MHz in the I branch and only 20 MHz in the Q. However, I always saw signal parts in each other and while debugging I found that I even see (small) 10 MHz in the Q branch when I connect it only to a voltage source supplying cos(2pi fc t)sin(2pi fi t).

In the end I ended up with a trivial testbench like this:

The "mixer_mult" is a Verilog-A model and only contains "V(out) <+ V(in) * V(lo);". However, the effects are similar when I replace it with ideal switches using "switch" from analogLib.

The time domain shows a small signal which to my understanding should only contain the RF image. However, examining the spectrum it is confirmed that there is a peak at 10 MHz in the Q channel which is only 44dB less than the full 10 MHz in the I channel:

First I thought it may be the image rejection filter (although contradicting) but increasing its order even to 11 did not change anything.

So I went off to Simulink with the same setup and saw the peak also there. However, it was lower (-60dB). After decreasing the (fixed) step size to 100fs the peak in Simulink was reduced to -80dB. So I thought it is merely a simulation artefact, went back to Spectre and re-run the sim with reltol=1e-6, vabsol=1e-9, iabstol=1e-15. However, nothing changed (it got even slightly worse).

Well, -40dB is pretty high and about the spec so it's hard for me to believe that the simulator is having numerical issues.

And on top of that: How should I start simulating actual IQ crosstalk when not even in the ideal scenario, the leakage is "minus infinity"??

While I think that tran sim is the "golden reference" and I would like to see its results make sense;what is the "proper" way yo simulate I/Q crosstalk? I played around with "hb" but the results are even crazier, telling me that the 10MHz in the Q channel are just 14dB below the I channel ...

Thanks!!

Hello guys,

I have been looking for a storage element or something like that so that I can store the output value of my circuit (I have both verilog-AMS/A model of my circuit). Basically, after one-time simulation, I want to keep the value forever. 

I think it is very similar to a ROM or OTP. So I was wondering if anyone has implemented a ROM/OTP in Verilog-A/AMS. I would appreciate it if you could tell how you did it.

I couldn't find a proper script for saving a value in Verilog-AMS/A. The output value will be lost after turning the power supply off. 

Thank you in advance.

Hello,

I lost my fully configured ADE L state already multiple times (until I found out why) because of the following issue: I put my frequency generator into a cell and instantiate it as an instance in my main test bench.

The frequency generator circuit contains a bunch of vpulse from analogLib and the parameters are derived from CDF parameters using pPar, e.g., 1/pPar("param_flo"). This allows me to create a single block supporting 50%, 25% duty cycle clocks with different delays etc. The frequency itself is a design variable in ADE L and is supplied as a parameter to the instance.

Now when I select pss Analysis problems start: The values in the "Fundamental Tones" box contain all * Nan *. Additionally, the CIW displays the following messages:

*WARNING* "lineage" not defined for CDF pPar function

It seems that ADE L is unable to resolve the frequency when it is passed as a CDF parameter. That wouldn't be a big deal for me if I could at least edit it. But editing the tones is not possible; all fields are greyed. However, it seems that it is still possible to simulate by just manually entering the fundamental tone. Now when I exit ADE L and confirm to save the state this seems to be buggy: Sometimes ADE L would not quit and sometimes I get messages like in the CIW:

WARNING (ADE-1071): Cellview spectre_state1 of type nil already exists.
Simulation design variables differ from those on the cellView,
they have been saved in the file "/tmp/saved-design-variables".
To save future changes, copy variables to cellView before exiting.

So far so good. However, when I want to reload the state, I get:

 (nil name "6" fundName "flo180" freqVar "1/(1/pPar("flo")-0)" freq "* Nan *" signal "Moderate" srcId "logen:V9" maxHarms "3" freqIndex "freq" oversample "1")
                                                     ^^^
SYNTAX ERROR found at line 2 column 54 of file /home/simulator/rx/tb_rf_iq/spectre_state2/rfstim.state
*Error* lineread/read: syntax error encountered in input

and the whole ADE window is empty with all information lost.

Is there a proper way to do this?

Thanks!

Hello! Is it possible to set somewhere the default options for the Selection Protection feature in Layout XL (the ones under "Edit->Select->Selection Protection Options...")?

Every time I open a new layout window I need to set these, which becomes cumbersome.

I tried looking on the .cdsenv settings but had no luck. In case there are no variables to control these, is there any way to set them through skill? For instance, I tried the following but it doesn't work:

procedure( mySetSelProtectionHighlight()
    geSetSelProtectionHighlightOptionForm()
    hiiSetCurrentForm('_geProtectOptionsForm)
    _geProtectOptionsForm->geHlWidth->value= "thin"
    hiFormDone(_geProtectOptionsForm)
);

...I'm interested to know if the latter approach for settings things via code would work, as it would allow us to automate many other things!

Thanks in advance,

Jorge.

Folks,

I am using Virtuoso (v 6.1.7). I'm making a lot of slotline structures in BEOL metals. I'd like to be able to simply draw a polygon on a given layer, then lay down a meandered wire of the appropriate width and length on another layer, and then subtract this wire or path from the larger polygon to produce a meandered slotline of a specific length.

Is anyone aware of a way to do this. To date I have been using the chop command to do this, but it's error-prone and quite time consuming for complex geometries.

Regards,

JW

Hi-

 I am having problems in using ADE-XL due to the verilog-A compiling issue. In the beginning of simulation,  the simulator re-compiles every single verilog-A block in the schematic which takes a lot of time as single block consumes ~5min to compile. I know that this is not the case for ADE-L. Although I found similar issue that was posted earlier (https://community.cadence.com/cadence_technology_forums/f/38/t/20866), I couldn't get to the linked solution (Solution 11603330) as I didn't have the permission. So, I asked of of University's department staff who had permission to look it up but he said that the page was expired. It would be appreciated if I could get some help with this issue. I am using IC6.1.5-64b.500.9 .

Thanks,

Hello, I have two questions about the generate physical hierarchy of the floorplanner tool.

1. In "generate physical hierarchy", there are always some blocks that have Param Changed indicated as YES. They are set to regenerate, even when they have just been generated. What can cause this? The soft-block parameters have not been changed, especially not if you run "generate physical hierarchy" two times in a row.
2. I use the force descend feature on a certain block. Is there a way to generate the physical hierarchy from the block I descend in?

Hello, 

I wanted to modify my extracted netlist and replace some transistors with their Verilog-a models. I have tried but it gave some error as "the cellview was modified..."  (I cannot specify Verilog-a model is used in config view) 

I appreciate your help on this matter. 

Thanks.

Dear Andrew,

I am using gpdk045 MOSFET transistor in cadence Schematic editor. Here 45nm is the technology node or gate length ?. I require to know both the gate length (Lg) and effective channel length (Lch) of the MOSFET. Could you please give some information on this?

Note : Lch = Lg-2Xd,

Xd - lateral diffusion from Source/Drain.

Thanks and Regards,

K. R. Pasupathy