Hello all,

I have a GDS layout previously designed in SoC encounter, I want to import it in Virtuoso but I don't have a layer map provided with PDK (I'm using Nangate Open Cell Library 45nm). I now have two files; a technology file provided with PDK and a streamOut.map file generated from GDS export in Encounter.

Here is the technology file:

---------------

Hi there,

I characterized custom cells for different corners and now want to create a verilog model for each corner. Although timings in the *.lib-file are totally different, path delay in all verilog models stay zero.
Here are the steps I did to create the models:

liberate > read_library lib/SUBVT28CORE_1.0_1.0_0_0_25_ecsm.lib

Command line arguments: none.
ALTOSHOME set to '/sct/homes3/cadence/liberate-15.14hf070'.
Server ID : T20170228092209088037S0008335
liberate > read_library lib/SUBVT28CORE_1.0_1.0_0_0_25_ecsm.lib
Reading 'lib/SUBVT28CORE_1.0_1.0_0_0_25_ecsm.lib' ...
//LIBERATE parameter "enable_command_history" set to "0"
LIBERATE parameter "slew_lower_rise" set to "0.3"
LIBERATE parameter "slew_lower_fall" set to "0.3"
LIBERATE parameter "slew_upper_rise" set to "0.7"
LIBERATE parameter "slew_upper_fall" set to "0.7"
LIBERATE parameter "measure_slew_lower_rise" set to "0.3"
LIBERATE parameter "measure_slew_lower_fall" set to "0.3"
LIBERATE parameter "measure_slew_upper_rise" set to "0.7"
LIBERATE parameter "measure_slew_upper_fall" set to "0.7"
LIBERATE parameter "delay_inp_rise" set to "0.5"
LIBERATE parameter "delay_inp_fall" set to "0.5"
LIBERATE parameter "delay_out_rise" set to "0.5"
LIBERATE parameter "delay_out_fall" set to "0.5"
Library read successfully.
1

liberate > write_verilog my.v
Writing Verilog to my.v
Writing Verilog for cell INV_X1

Looking at my.v gives:

// type:  
`timescale 1ns/10ps
`celldefine
module INV_X1 (Z, A);
        output Z;
        input A;

        // Function
        not (Z, A);

        // Timing
        specify
                (A => Z) = 0;
        endspecify
endmodule
`endcelldefine

Instead of the timing specification, I would expect something like this (example from 65nm lib):

   specify
     // delay parameters
     specparam
       tpllh$A$Z = 97:97:97,
       tphhl$A$Z = 74:74:74;

     // path delays
     (A *> Z) = (tpllh$A$Z, tphhl$A$Z);

   endspecify

Why does liberate skip the timing annotation?  Am I missing out some necessary configuration?

Thanks in advance and best regards,
Marten

Hello all,

I want to test a digital chip on Cadence Spectre using its extracted SPICE netlist from Calibre PEX. The chip has a bit stream of 128 bits as input and its outputs are:  a digital bit stream of 128 bits and an analog signal. So what is the best way to generate the input bit stream ?

I found a way using vbit source and loading a bit stream to it using a txt file, but is there a better way ?

Hello all,

I have a design in Cadence Virtuoso (originally designed in SoC Encounter using NangateOpenCellLibrary 45nm std cells), when I try to open any std cell in the design schematic, I get these warnings and the std cell schematic open having all pins (inputs and outputs) marked as "unbound"

*WARNING* (DB-270337): Failed to open cellView (ipin symbol) from lib (NangateOpenCellLibrary) in 'r' mode because cellview does not exist.
*WARNING* (DB-270337): Failed to open cellView (opin symbol) from lib (NangateOpenCellLibrary) in 'r' mode because cellview does not exist.
*WARNING* Missing Masters:
Library Cell View 
NangateOpenCellLibrary ipin symbol 
NangateOpenCellLibrary opin symbol

and when I try to run LVS (between imported GDS layout and verilog netlist exported from Encounter), I get a bunch of these errors:


ERROR (OSSHNL-366): Instance 'I4' in cellview 'NangteOpenCellLibrary/AND2_X4/schematic' is bound to placed master 'NangateOpenCellLibrary/ipin/symbol'.
However, OSS has determined that it is not a valid placed master. Ensure that
cds.lib has entries for all the reference libraries and netlist again. Correct
this error and netlist again.

*WARNING* (DB-270337): Failed to open cellView (ipin symbol) from lib (NangateOpenCellLibrary) in 'r' mode because cellview does not exist.

*WARNING* (DB-270337): Failed to open cellView (ipin symbol) from lib (NangateOpenCellLibrary) in 'r' mode because cellview does not exist.
*WARNING* (DB-270337): Failed to open cellView (ipin symbol) from lib (NangateOpenCellLibrary) in 'r' mode because cellview does not exist.
*WARNING* (DB-270337): Failed to open cellView (ipin symbol) from lib (NangateOpenCellLibrary) in 'r' mode because cellview does not exist.


Any suggestions ?

I generated a physical verliog netlist for my design in Encounter using "saveNetlist design.v -phys -includePowerGround -includePhysicalInst". Here is the explanation of every attribute in this command:

-phys: Writes out physical cell instances, and inserts power and ground nets in the netlist. This is used for LVS and for designs with multiple supply voltages.

-includePowerGround:    Includes power and ground connections in the netlist file.

-includePhysicalInst:   Includes physical instances, such as fillers.

WhenI try to import this netlist in Virtuoso, I get these warnings for all std cells:

WARNING (VERILOGIN-111): Cannot connect the terminal VDD in symbol AOI211_X1 as it does not have a pin.
WARNING (VERILOGIN-111): Cannot connect the terminal VSS in symbol AOI211_X1 as it does not have a pin.
WARNING (VERILOGIN-551): Number of pins on symbol DFF_X2 in library NangateOpenCellLibrary differ from the number of ports in
the HDL module description.

When I open the symbol of DFF_X2, there is no VDD and VSS symbol, so should I update the symbol of all std cells manually to have the VDD and VSS symbols ?

(I can find "VDD!" and "VSS!" pins in DFF_X2 schematic but not in its symbol)

Additionally, I get these warnings for FILLER cells:

WARNING (VERILOGIN-72): Could not find the symbol master for the instance FILLER_5. Therefore the functional
view will not have this instance.

And again there is no symbol view for FILLER cells in the std cell library.

Since, all std cells schematics have VDD! and VSS! pins but their symbols don't, was this made so that Virtuoso power these pins virtually without an explicit power source and ground ? or this is wrong and I have to update all symbols manually ?

Finally, power and ground are called "VDD" and "VSS" respectively in my verilog netlist, however they are written as "VDD!" and "VSS!" in all std cells schematics. So what is the difference between "VDD" and "VDD!" ?

Thanks

Hi everybaby,

I am getting extrange behabiour in assura. I have 2 digital blocks A and B sintetized independently and  we have added prefixes A_... B_... to the corresponding subcircuits in to avoid problems when put together.

When placed together, they have independent power rails.

The LVS are clean if run independently but when they are put together i get a lot of parameter mismatch in cells made up by feedthrough cells from the std. library of the technology.

Suppose i have the cells feed1, feed2...feedn from the standard lib. When I open the LVS Debug Env.  and i open the mismatches it shows that what is in the schematic feed2 is in the layout feed7 (for example). Like this many other similar.

I found out the ambiguities message during the LVS run as weel.

For me looks like assura is mixing the feedthrough cells. Since  the feed cells in a block are all connected to the same VDD and GND the circuits match (instances, nets...) but the parameters not.

The autoswappin option is "off".

I hope somebody can elucidate some solution the problem or hint.

Best regards,

Manuel

Hello! Is it possible to tell Spectre to use different models for the same devices in different modules? Our design kit has standard and "PRE_SIMU" models (=include contact-to-poly caps and parasitic contact and gate resistances) for the MOS devices, and we would like to use these PRE_SIMU models only for the devices in specific modules, at different moments in the design cycle:

-In the early design phases, use PRE_SIMU models only for the critical blocks in the system, and standard for the rest (speeds up simulation time)
-In the later design phases, use PEX views for the already laid-out critical blocks, and PRE_SIMU models for everything else not yet laid-out.

Currently all I can do is define these models globally for all the devices using the Model Library Setup window (need just to include a section from the model libraries). However, as soon as I use PEX views, I need to switch back to the standard models, as using PRE_SIMU globally would yield incorrect results due to double-counting of parasitics in the modules with PEX views. Thus the accuracy of our simulations gets compromised as we proceed into the implementation cycle and start to add PEX views.

...any ideas on how to overcome this problem?

Thanks in advance for any help.

Jorge.

Hello all,

I imported a verilog netlist for a layout previously designed in Encounter. When I try to open the schematic and hit check&save, I get these errors:

Error: Net "v_CALCULATION_CNTR<7:0>" shorted to net "N5512,N5511,N5510,N5509,N5508,N5507,N5506,SYNOPSY S_UNCONNECTED__0".
Error: (DB-270004): Illegal bus reference - Can't tap "<N5507>" from net "v_CALCULATION_CNTR<7:0>".
Error: (DB-270004): Illegal bus reference - Can't tap "<N5512>" from net "v_CALCULATION_CNTR<7:0>".
Error: (DB-270004): Illegal bus reference - Can't tap "<N5509>" from net "v_CALCULATION_CNTR<7:0>".
Error: (DB-270004): Illegal bus reference - Can't tap "<N5508>" from net "v_CALCULATION_CNTR<7:0>".
Error: (DB-270004): Illegal bus reference - Can't tap "<N5511>" from net "v_CALCULATION_CNTR<7:0>".
Error: (DB-270004): Illegal bus reference - Can't tap "<N5510>" from net "v_CALCULATION_CNTR<7:0>".
Error: (DB-270004): Illegal bus reference - Can't tap "<N5506>" from net "v_CALCULATION_CNTR<7:0>".
INFO (SCH-1172): There were 8 errors and 0 warnings found in "NangateOpenCellLibrary key_expansion_KEY_SIZE0 schematic".

Moreover, I can see lots of unconnected wires like the attached picture



This verilog netlist was exported from SoC Encounter from a layout with no geometry or connectivity violations. 

Any suggestions ?

EDIT: the unconnected wires are probably due to some floating output pins of std cells that are not used in the design and I don't see errors complaining about them.

Hi, in the layout dynamic selection assistant, is there an option to change the default text from light gray on white to black on white for all lines in the DSA (not just the selected line), for easier readability?  Also, is there a way to cut/paste the DSA text when in "freeze" state to a file or to CDS.log?  Thanks.

Hi,

Is it somehow possible to store design variables of a cell in a config-like cellview or file?

Here is what I mean: Suppose I design a simple opamp for I which create a triangle symbol view and use it in many other places. Now when I design the amplifier I have all the widths, lengths, bias currents in my ADE L view as Design Variables. I can sweep them until they match and then I fix them. Now, 2 weeks later I need to change the amplifier. I need to replace all the static values by design variables, design the amplifier and re-replace the values again with their static values.

This is extremely error prone (and I always make mistakes), particularly since so many values are interrelates (e.g. the widths in a differential configuration are the same and the biasing branches are just some multiple).

What I envison is some sort of pPar which takes the actual values from a config file or config cell view. Then it's also way easier to keep an overview on the design and archive specs.

What I do not want: Store the values in an scs file and use "Simulation files". It just does not work because ADE L always imports the design variables into the window and then simulation fails if if they are not set (and if they are set, they overwrite the values from the scs file). Supposedly copyDesignVarsFromCellview should fix this (see ) but this is just ignored. (Even if, I would not consider it a clean solution

hi

my question is regarding BER testing. I want to check the BER for OOK modulator/demodulator.  I tried to find (in forum discussions) the setup/instances that may help to make setup for BER testing. Kindly guide is there any instance/setup avaialbe?

Thanks

Hello all,

I know this has been addressed several times before as I've searched the forum before actually asking this question but I have tried the solutions but nothing seems to work. I'm trying to characterize an NMOS using the gm/Id technique which requires me to save the intrinsic parameters such as gm,gds,fT while the Vgs is being swept for a range of values. For this I have used the save NM0:all statement, saved it in a .scs file and have included it in the netlist as shown below. Spectre then gave a warning saying the following:

"WARNING: subcktInst:all is not supported.
WARNING (SPECTRE-8287): Ignoring invalid item `NM0:all' in save statement."

I then followed Andrew Beckett's advice on another post about saving Subcircuit stuff as per the following link [1] , and changed the save statement to save NM0.nm_hp:all, in which Spectre gives the following warning:-

"WARNING (SPECTRE-8282): `NM0.nm_hp' is not a device or subcircuit instance name.
WARNING (SPECTRE-8287): Ignoring invalid item `NM0.nm_hp:all' in save statement. "

I can confirm  that the transistor I am using is a subcircuit with the name nm_hp as the model file has the following lines, 

subckt nm_hp ( d g s b )
parameters

My question is, what am I doing wrong here? I have included all the appropriate model files and netlists and nothing seems to work. I can't for the life of me figure out what's wrong. I have attached the netlist below. Whelp?

Netlist:-

NM0 (vdd! net2 0 vdd!) nm_hp w=(4u) l=(130n) as=1.36p ad=1.36p ps=8.68u \
pd=8.68u m=1 sa=340n sb=340n sd=0 nf=1
V1 (vdd! 0) vsource dc=600.0m type=dc
V0 (net2 0) vsource dc=600.0m type=dc
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
checklimitdest=psf 
dcOp dc write="spectre.dc" maxiters=150 maxsteps=10000 annotate=status
dcOpInfo info what=oppoint where=rawfile
dc dc dev=V0 param=dc start=0.2 stop=1.2 step=0.05 oppoint=rawfile \
maxiters=150 maxsteps=10000 annotate=status
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
save NM0.nm_hp:all
saveOptions options save=allpub

[1] community.cadence.com/.../26938;ReplyToContentTypeID=0

I am trying to make a model and use it for ideal diode from analogLib library. However, I don't know how to modify the built-in potential (or forward voltage) of the diode. I tried to add VJ variable and set it to a small value like 0.1V. However, from I-V characteristic of simulation, it doesn't seem to have any effect on forward voltage at all. The built-in potential from the simulation is about 650mV. 

Can anybody tell me how to do that? I want the diode is like ideal (zero forward voltage and infinite slope).

Here is the model file I used (diode.scs):

simulator lang=spice

.model schottky D (LEVEL = 3 IS=1p RS=0 BV=40.0 IBV=1p VJ=0.1 CJO=0 M=0.5 N=1 TT=0 )

Hi all:

I'm at QRC stage now where I have encountered this extraction problem:

Cadence Extraction QRC - 64-bit Parasitic Extractor - Version 13.2.0-s451
Tue Jul 22 19:35:08 PDT 2014
-----------------------------------------------------------------------------------------------------------
Copyright 2013 Cadence Design Systems, Inc.

INFO (EXTQRCXOPT-243) : For Assura inputs, if the "output_setup -directory_name" option was not
specified, it is automatically set to the input directory.
WARNING (LBRCXM-624): Warning [input]: Line 8: 'well' statement is ignored in ICT file line.

WARNING (LBRCXM-624): Warning [input]: Line 10: 'well' statement is ignored in ICT file line.

INFO (LBRCXM-624): No temperature processing will occur for the layer CONT, because this layerhas no Tc1 and Tc2.

INFO (LBRCXM-624): No temperature processing will occur for the layer CONT, because this layerhas no Tc1 and Tc2.

INFO (LBRCXM-624): No temperature processing will occur for the layer VIA1, because this layerhas no Tc1 and Tc2.

INFO (LBRCXM-624): No temperature processing will occur for the layer VIA2, because this layerhas no Tc1 and Tc2.

INFO (LBRCXM-624): No temperature processing will occur for the layer VIA3, because this layerhas no Tc1 and Tc2.

INFO (LBRCXM-624): No temperature processing will occur for the layer VIA4, because this layerhas no Tc1 and Tc2.

INFO (LBRCXM-624): No temperature processing will occur for the layer VIAF, because this layerhas no Tc1 and Tc2.

INFO (LBRCXM-624): No temperature processing will occur for the layer VIAF, because this layerhas no Tc1 and Tc2.

INFO (LBRCXU-108): Starting

/opt/cadence/installs/ASSURA41/tools.lnx86/assura/bin/rcxToDfII /home/cds/ee642_project_umais/d1/__qrc.rcx_cmd -t -f /home/cds/ee642_project_umais/d1/extview.tmp -w /home/cds/ee642_project_umais/d1 -cdslib /home/cds/ee642_project_umais/cds.lib
Virtuoso Framework License (111) was checked out successfully. Total checkout time was 0.05s.
@(#)$CDS: rcxToDfII_64 version av4.1:Production:dfII6.1.6-64b:IC6.1.6-64b.101 08/06/2013 14:01 (sjfnl785) $
sub-version 4.1_USR4, integ signature 2013-08-06-1301

run on cdspc from /opt/cadence/installs/ASSURA41/tools.lnx86/assura/bin/64bit/rcxToDfII on Sun Mar 12 10:42:10 2017

*WARNING* Technology must be specified!
*LF-INFO* Loading cmos150/cmos150.skill/cmos150_cdfCbks.il done
*LF-INFO* cmos150 libInit.il loaded successfully.
*LF-INFO* Loading cmos150hv/cmos150hv.skill/cmos150hv_cdfCbks.il done
*LF-INFO* cmos150hv libInit.il loaded successfully.
*ERROR* No library model for device "nmosld40v_4 auLvs cmos150hv".
*WARNING* (DB-270211): dbOpenCellViewByType: Failed to open cellview (nmosld40v_4 auLvs) from lib (cmos150hv) in 'r' mode because cellview does not exist, or cellview type is not recognized by dbOpenCellViewByType.
*WARNING* (DB-220704): The Pcell super master: cmos150/break/auLvs is not a SKILL super master.
The usage of non-SKILL Pcells in Virtuoso is not a supported feature.
*WARNING* (DB-220704): The Pcell super master: cmos150/make/auLvs is not a SKILL super master.
The usage of non-SKILL Pcells in Virtuoso is not a supported feature.

ERROR: Assura is terminating because some library models do not exist.
Your rules and your dfII model libraries are inconsistent.
Assura requires all library models in the rule file be present
in the database when running rcx with the "extracted_view"
option.

INFO (LBRCXU-111): Warning /opt/cadence/installs/ASSURA41/tools.lnx86/assura/bin/rcxToDfII exit with bad status

INFO (LBRCXU-112): Warning Status 256

INFO (LBRCXU-113): Warning QRC execution terminated

***** aveng fork terminated abnormally *****

If anyone has fixed such an error or knows how please help

Hi,

when I execute following commands:

analysis('noise ?anaName "noise1")

analysis('noise ?anaName "noise2")

ocnDisplay('analysis)

I see that anaName is saved and thus the 2nd analysis is overwriting my first. Is there anythin I did wrong? Or isn't that supported by ocean (I think in a spectre include file will do)...

Virtuoso 6.1.6-64b

Best Regards,

leo

what is the equation to find total capacitance?

how to replace a capacitor by mosfet and how to prove them they are equal?

Hi All, 

 Due to my mistake I set up a design library as a technology library and built quite some designs in it. Is there any way that I can change it back to a design library? I played with the Technology file manager but found no way to do that...

  Virtuoso version: 6.1.6

Best regards,

Qilong 

Hi! I recently updated to IC617 and now in Viva a window appears with the variables values whenever I hover the mouse over the trace names. I've been trying to disable this feature with no luck (menus, cdsenv settings). How can I achieve this? In attachment a snapshot of what I mean.

Thanks in advance for any help!

Jorge.

Hello! Trying to debug DC convergence issues I came across the "Spectre and APS Non-Convergence Debug Guide", where most solutions involve using "options statements". How and where in ADE-L do I specify these options statements for the simulator to catch them? I tried many options without success:

-Make an .scs file and include it with the simulation libraries
-Make an .scs file and include it in the "paramSet" directive
-Use the "user command-line options" field in the Setup->Environment menu
-Use the "Additional arguments" field in the Simulation->Options->Analog menu
-Use the "additionalParams" field in the tran analisys "Misc" tab

(...side question: is there any document where the differences between all these places for specifying options are explained?!)

Thanks in advance for any help!
Cheers,
Jorge.


P.S. I'm referring to this document: AppNote_nonConvergence_v2.pdf

Folks,

I am using IC6.1.7 (64b) on Linux, Layout suite L. I'm looking for documentation on the use of the Create Via dialog. Specifically, I cannot locate any information on using the "Shapes(s)" or "Drawn Area" modes of operation. Ideally I could use this tool to produce via arrays to fill a variety of polygons.

In addition, I've tried editing (via the Options button) the "User Min Cut Spacing" to adhere to my PDK's via array spacing values for larger arrays (more than 3 vias), but the tool will always revert to the standard 2-via spacing (which is less than the value required for larger arrays). I can, post-facto, modify these spacing constraints in the object created by the tool, but I'm wondering if there is a way to fix this before placing the via object?

Regards,

JW