Hi,

I am a beginner in ocean. I have the following ocean script which reports the source current of transistor M3.

;*****************************

openResults("~/simulation/TEST_OPAMP_POLY_TB/spectre/schematic/psf/")
p=outfile("/home/mt2775_loc/simulation/TEST_OPAMP_POLY_TB/spectre/schematic/netlist/resultsSpectre.txt" "w")

fprintf(p, "Hello World! to make sure it is working\n" )
selectResult('dcOp)

fprintf(p,"%f",i("/I0/M3/S"))

;*****************************

I also know if I use outputs() command, all DC values will be printed out. I need a such command fprintf(p,"%f", outputs()). 

The question is that which command can print all DC values into the file (instead of calling function "fprintf" for each one by one like above) ? If I need to use a loop would you please let me for that.

Thank for your help

Mohammad 

Hello,

I am working on a project where I need to add some custom layers for layout. In order not to mess with the original Kit, I want to make a copy of it and do all the modifications  to that copy such that any changes in it does not affect the original kit. 

Any thoughts?

Thanks 

I am incorporating a device (memrsitor) in my layout that is not defined in the kit. I was thinking of representing the device by a layer that is not used in my design. However, this layer will have its own design rules that are different from the ones I want to set for my memristor?

So, I was thinking of using a layer that does not affect affect the DRC tool (the DRC does not show an error no matter where it is placed) or make the tool ignore the design rules for a specific layer and use that layer to represent the memristor. Is that even possible?

Any thoughts on that issue will be appreciated. 

Hello,

I am using version IC6.1.6-64b.500.11.

In layout editor, I would like to create a continuous (metal) routing (or path) which consists of pieces with different width. When I create a routing by pressing "p", the width is the same for each sub-part of the continuous path. Would it be possible to have what I want?

Many thanks in advance.

Best regards,

Can

Hi to everyone!

We're looking for a solution for an apparently simple problem.

When starting a simulation with spectre, we want to look into the results right from the beginning.
We want to do this to evaluate the simulation immediately. This is sometimes necessary for long-lasting simulations to stop them if they are going into the wrong direction.

However, spectre seems to update the saved simulation data periodically in fixed time frames.
Thus, for long simulations we have to wait for a very long time to be able to take a first look at our saved outputs. Is there a command or a flag for spectre (MMSIM) that I can set to shorten this time frame?

We spent a lot of time searching for this option in the Cadence manuals without success. We are using IC6.1.6 and MMSIM14.1 but the problem is version independent since older and newer releases show same behavior in our setup.

Thank you for your help in advance.

On trying to run any simulation in ADEXL I am getting ADEXL 1921 error (failed to start job after 3 attempts. Possible reasons could be ........).

Also on trying to execute virtuoso -nograph I am getting the following error:

"Xlib: connection to "servername:80.0"refused by server

Xlib: No protocol specified

*WARNING* Could not open display servername: 80. If no server is running for this display, please remove the file /tmp/.X11-unix/X80/

Trying another display ........................

*WARNING* unable to connect to a non graphical X Window Display server.

My version is IC6.1.5-64b.500.15. ADEXL was working earlier for me and still does for other users in our server. The issue is only with my account apparently.

I tried running virtuoso from a new folder using some basic cdsenv cdsinit files as well.  I can start up the virtuoso GUI using virtuoso &  and the normal ADE runs just fine. We ssh into the server with X11 forwarding.

Any ideas regarding what changed and how could I rectify this issue?

I am trying to develop a simple transistor model in which I could just vary drain-source and gate-source voltage and calculate the drain current. I have drain current equation as well as the parameters values on which it is dependent. Can I write my own SPICE model (without any .MODEL statement) with this information and run it with spectre/hspice in ADE ?. Any examples for such models ?

Farhan

Hello forums,

1) I have an age old problem that I know not how to resolve. I have a layout and I created the spice netlist from it using PVS ERC. I cleaned up the resulting netlist (by removing the coordinates $X and $Y) and I added it to a library. I created the auCdl and spectre views and added the required commands in the .simrc file. Then I tried simulating the cell, but I get the error that the "Instance M0 has no valid master". It happens for all transistors in the spice netlist. I do not know how to fix it. I can do spiceIn, create the schematic and then use it to simulate, but I wish to simulate the spice in spectre instead of going through that longwinded route. Could someone please tell me what I am doing wrong? For the sake of information, this is my spice netlist and the library description:

*******************************************
* Sub cell: xx
*******************************************
.subckt xx I ZN power ground
** N=5 EP=4 FDC=12
M0 ZN I ground ground nch_hvt_dnw L=6e-08 W=3.9e-07
M1 ground I ZN ground nch_hvt_dnw L=6e-08 W=3.9e-07
M2 ZN I ground ground nch_hvt_dnw L=6e-08 W=3.9e-07
M3 ground I ZN ground nch_hvt_dnw L=6e-08 W=3.9e-07
M4 ZN I ground ground nch_hvt_dnw L=6e-08 W=3.9e-07
M5 ground I ZN ground nch_hvt_dnw L=6e-08 W=3.9e-07
M6 ZN I power power pch_hvt L=6e-08 W=5.2e-07
M7 power I ZN power pch_hvt L=6e-08 W=5.2e-07
M8 ZN I power power pch_hvt L=6e-08 W=5.2e-07
M9 power I ZN power pch_hvt L=6e-08 W=5.2e-07
M10 ZN I power power pch_hvt L=6e-08 W=5.2e-07
M11 power I ZN power pch_hvt L=6e-08 W=5.2e-07
.ends xx

//-------------------------------------------------------------
//Typical case (typical parasitics values)
//-------------------------------------------------------------
section CDL_TYP
simulator lang=spice insensitive=yes
.include "./csl_all.inc"
.include "./csl_hvt_all.inc"
.include "./csl_lvt_all.inc"
simulator lang=spectre insensitive=yes
endsection CDL_TYP

2) When I generate the netlist using PVS ERC, it gives the individual transistors based on their location. Is there any way (skill function) so that the mosfets can be smashed and I can get a netlist which includes the principal transistors with the number of fingers rather than each finger listed as an individual transistor?

Thanks a lot in advance,

Raghavan

Hello,
I created a symbol in Virtuoso 6.16 and wrote a SPICE model for it and added spectre stop view in cell view. Now when I try to simulate (MMSIM 13) it I don't get any error but the current through the behavioral source (bsource) is incorrect. However, the equations in my functions are correct. What could be the reason for it? is it because of the if..else conditions?.  Kindly see the example of my model below.

**myFunctions
simulator lang=spectre
real myfunc1( real A, real B, real C ) {
    return A + B + C;
    }

real myfunc2( real A, real B, real C ) {
    return A - B - C;
    }
    
real myfunc3( real A, real B, real C ) {
   return A * B * C;
   }

**myModel
simulator lang=spice

subckt myModel X Y Z
.param
+W=100u L=100u
+a1 = 1u
+a2 = 2u
    *Behavioral current source between X and Z node
    cccs1 X Z bsource i=(W/L) * (if(V(Y, Z) <= 0.3, myfunc1(A, B, C), if(V(Y, Z) > 0.3 & V(Y, Z) < 0.7, myfunc2(A, B, C), myfunc3(A, B, C))))
    *resistance between X and Z node
    R X Z 10e9

.ends

I want to run DRC a a specific cell. 

first, I used to run it as: IBMPDK-> checking > calibre DRC and a form would pop up where I can define my BEOL_stack. Now I am running on a copy of the kit and when i go through the same procedure (IBMPDK-> checking > calibre DRC), nothing shows up (no window pops up). 

So, I decided to do it from Calibre->DRC and the calibre window (calibre interactive) poped up but without that form where i set the environmental variables (ex: BEOL_stack). So,  when I run it ,it shows that error<

Error while compiling rules file /data1/IBM_PDK/cmos10lpe/V1.5.0.0RF/Calibre/DRC/cmos10lpe.drc.cal:
Error USER1 on line 102 of $TECHDIR/DRC/Include/cmos10lpe_config.drc.cal - ENVIRONMENT variable $BEOL_STACK must be set to one of:
5_00_01_00_LB,
5_02_00_00_LB,
6_00_01_00_LB,
4_02_00_00_LB,
4_03_00_00_LB,
4_20_01_00_LB,
4_00_02_00_LB,
5_00_02_00_LB,
6_00_02_00_LB,
4_30_01_00_LB,
6_02_00_00_LB,
6_10_01_00_LB,
5_00_01_10_LB,
6_00_01_10_LB,
4_01_00_01_LD,
5_01_00_01_LD,
4_01_00_01_LB,
5_01_00_01_LB

Can some one help me with that?

Also, I want to understand what a runset mean?

Thanks

Hello,

I am using version IC6.1.6-64b.500.11.

I am creating a layout with some SKILL instructions. I would like to add a pin by defining some parameters like terminal name, I/O type etc. From what I have found from different sources, I got close to my goal with the following part of my code:

labelID = dbCreateLabel(cv list("M1" "label") 0.5:0.5 "testNet" "centerCenter" "R0" "stick" 1) ;this line seems not so critical but creates a label on the layout that makes it easy to observe the terminal names on the pins

netID = dbCreateNet(cv "testNet")

figID = dbCreateRect(cv list("M1" "label") list(0.0:0.0 1.0:1.0))

pinID = dbCreatePin(netID figID);

However, I was not able to change the I/O type. I have tried the following; however, when I open the layout view and check the properties of the square pin, the I/O type appears to be unused:

pinID~>direction="inputOutput"

Could you please help me regarding this issue?

One additional question: How can I observe the list of the attributes and parameters of an object (like rectangle, path etc.) that I can modify in SKILL?

Many thanks in advance.

Best regards,

Can

Hi

I am using IC6.1.6-64b.500.8, Virtuoso ADEL and ADEXL. I am using a technology file from Taiwan Semicon...' and standard VT devices in my circuit.

When I see the Model file (tech.scs) it has many different model cards with different numbers like  "model pch bsim4 { 1: type=p ...." 2: type pch, 4: type pch....etc."  

Q1.  How to find which  Model card is used for the simulation for each device (ex. two Model cards for two MOSFETs) and it's location during or after simulation??

Q2. If the W/L of MOSFET is changed then will the Model card number (1: type=p  to   2: type pch or 4: type pch....etc)  also changed ??

Actually,  I need to analyse the variation in different variables (VTH0 variation, U0 mobility, Toxe etc...) of Model card used in simulation. Therefore I must know which model cards are used for the simulation for each devices (MOSFET) for each device width W and length L.

Any help is highly appreciated. 

Dear all

I want to design a vccs to implement this function:

I(y)<+ tanh(V(x));

I have done that using a verilogA model and I connect it in the cadence circuit which is as in the attached file, the model itself works fine but I want it to act as a real electronic component when connected to the circuit, by means when I change the output resistance the output current from this component should be changed accordingly as in the real electrical circuits, how can I do that, the current is always fixed and not affected by the resistor next to it. Because at the end I'll do a lab work by which I will use a similar component .

I read about bsource but I did not find it in any of the libraries !

any suggestion will be appreciated.

Thank you

Dear all,

I'm using PSS for rectifier simulation and try to look at the voltage and currents in steady state. I'm trying to improve the accuracy of the PSS and try to get the same results as in the transient simulation (after it settled).

Currently, I use the Harmonic Balance mode. However, I heard Shooting Newton is better as it is only a wrapper for transient simulation. But, personally, I find HB to be more stable. From reading the user manual, when the over_sampling factor is set to be very big, the accuracy is very high. But how big should we set to this over_sampling factor to be? The higher, the better? Also, is there any additional way to improve the accuracy of the pss simulation? max_iters?

Also, does PSS support multi-thread? How to activate this?

I found PSS HB sometimes giving the correct results (i.e. the same as transient), other times not giving the correct result. Is this because I'm not setting the convergence parameters properly?

I know the port element in cadence only provides power in reference to 50 Ohm. Could you please recommend a solution if we have to use a port that has complex impedance? For example, a rectifier driven by custom antenna whose impedance conjugatively matched to the rectifier.

I use mmsim14 + ic616.

Thank you very much,

Menghan

Hi,

I am using ICADV12.2 ADE Assembler. Every time I run a simulation, a ViewFile-Window opens showing the spectre.out file. How can I prevent this? I do not want to show this file every time I run a simulation.

Kind regards
Sascha

Hello everyone,

PROBLEM EXPLANATION

I am facing a strange problem. First of all, I am using ICFB (a very old version).

I have a very simple cell made of 4 transistor. This cell has a schematic view, a layout and an extracted view.

I can do simulations with the schematic view (everything work as expected) using ADE and Spice. Then, the DRC and LVS on the layout give no error. 

At this point, I want to run the exact same simulation on the extracted view.

In order to do so, I go to Setup->Environment and in the Switch View List I insert "extracted" as the first element.

I then run the simulation and the result is the _exact opposite waveform_ at the output. (the block is supposed to act as a "digital" block, so I really mean that where I expect to see a "1" I get "0" and viceversa).

Now, if I check the netlists that are produced after the schematic and extracted simulations (in ADE, I go to Simulation -> Netlist -> Display Final) they don't exactly match:

I want to use the DEFT feature in Cadence. I went to tool>technology file manager> and then this little form showed up that has things like dump....etc. There should be DEFT under the edit option. I cannot find it, however. I checked the software package I have and DEFT seems to be installed. 

Any idea how I can handle this? I want to DEFT tool to show up in that form or in general I want to be able to use it. 

Thanks

SHerif

Hello,

Firstly, I use the following versions of the tools:

IC6.1.6-64b.500.11

Calibre nmLVS 2016.2_39.29

Calibre Quantus QRC

ADS 2012.08

My goal is to perform RC extraction on a layout (let’s say myLayout) that contains an inductor cell which is characterised with Momentum simulations. myLayout contains also other components like MOSFETS, resistors etc.

I simulate the integrated inductor with ADS Momentum and create the simulator cell views. Then I perform LVS on myLayout by providing a BOX rule file. Like that, the inductor is seen as a box. The LVS works without any problem on myLayout. However, I am not sure about the parasitic extraction with Calibre - Quantus QRC. In my opinion, the inductor cell should be blocked during the parasitic extraction since it is already extracted by ADS simulation. Then the model provided by ADS should be included in the extracted view created by Calibre QRC extraction. However, I am not sure how to perform this. I am not even sure if what I have in my mind is the best and known flow for the case I am having.

Could you please help me and provide the correct flow of this problem?

Thank you very much in advance.

Best regards,

Can

Hi,

I do not quite understand how the pss/pnoise jitter simulation works and if it is the right tool in the first place.

I generate a clock with a bunch of logic gates and flip flops and would like to assess what kind of jitter (in ps rms) I can expect at the output.

For a first testbench I use a simple vpulse creating a rectangular 100 MHz clock and a simple CMOS inverter.

I set up a pss simulation with:

• harmonic balance
• Beat Frequency 100M
• number of harmonics: 21

followed by pnose with:

• Absolute sweep
• From 1k to 10G
• Default sidebands
• Noise type: jitter
• Threshold value: 0
• Crossing direction: all

Is this the correct setup?

When I start this sim I sometimes get "No zerocrossing found". If it works, I can plot "Threshold Xing" for different "Event Time". What it this for?

Then I can plot Jee, Jc and Jcc, giving me all different results and I do not understand why I need to select the Event time or number of cycles.

For example, for the listed event times (look like random numbers to me), the total integrated jitter is 77ps, 191ps, 233fs, 228fs. Why is there such a huge spread and which number is expected to be the "correct" one?

Based on a quick back-on-the envelope calculation jitter should be around 150fs rms: I use 20ps rise and fall time and the total integrated noise of this inverter is around 7mVrms: 7mV/(1V/20ps) = 140fs.

So even if I get this right I wonder how I could simulate a clock generation circuit using a ring counter: Say, I use a 100 MHz clock, put it into 10 flip flops in feedback to get 10 MHz clock. Is this possible at all?

Thanks!

hi

I have a question regarding parametric analysis. I want to sweep two variables (in parallel) to find some optimum value. but i am facing the problem that it sweeps one variable while fixing the other; and after completing the 1st variable sweep; it takes next value of variable 2 and sweeps variable 1 again for complete range. so how can i made modifications in parametric analysis to sweep both variables in parallel.

Many Thanks