Hi everyone,

If I want to send to a file data from a particular mosfet parameter, say the mosfet current id, I can do: ocnPrint(?output "<path>/<filename.dat>" getData("M0:id"))

Now, what if I want to send the data resulted from an expression? For example:

gm\/gds   = (getData("M0:gm" ?result "dc") / getData("M0:gds" ?result "dc"))

plot(gm\/gds ?expr '( "gm/gds" ))

Should I put (getData("M0:gm" ?result "dc") / getData("M0:gds" ?result "dc")) in the field where I have  getData("M0:id") or it has to be in another way?

In addition to this, I have another question. If I use the parametric analysis to sweep any transistor parameter, say L, when saving to the file one on single data, like id, everything is ok. However, if I run the same analysis and I ask to save to the file several data the file is a mess. Only shows the swept variable for the first say 3 data leaving the rest unidentified.

I would to ask if there is anyway to get a more tidy file after running the paramAnalysis? In case there isn't, can I use some sort of loop to change the L parameter and save in a different file the data for each L?

Regards.

Thanks in advance.

Hi,

I wonder if there are any way to access design variables in ADEXL from a Verilog-A file during a transient simulation?

I am sweeping a design variable in my ADE-XL session and running several simulations in parallel. During the simulation, i use a Verilog-A script to read simulation data and store to a .csv file. 

The problem is that when i run the simulations in parallel, i dont know in which order the simulations will be finished and hence the order of the results in the CSV file. If i could write the value of the design variable under sweep together with the simulated data, i could determine the order of the simulations in post processing of the CSV file. 

In below for MWE, i read the voltages vin and vinp at the first timestep after 1ns. 

module datacollect(inp,inn);
input inp,inn;
electrical inp,inn;
integer file;
integer found=0;
analog begin
@(initial_step) begin
file=$fopen("path/temp_data.csv","a");
found=0;
end
if($realtime>1e-9)
begin
if(found==0)
begin
$fwrite(file,V(inp),",","V(inn),",",sweep_var),",");
found=1;
end
end
end
endmodule

Thanks

Hello,

I would like to do post-layout simulation of a design that uses standard cells by creating a spice compatible netlist  (to be able to use it with ELDO). 

The problem is that when I use the follwing sequence, a dspf netlist is created without the standard cell instances, only the parasitic capacitances.

So here's what I do (similar to what is advised in the DK QRC path)

1. Generate the GDS.

2. Generate the CDL.

3. Run PVS LVS using this command

pvs -lvs -hcell xcells -top_cell CellName  -gds CellName.gds  -source_top_cell CellName -source_cdl CellName.cdl -spice CellName.spi -qrc_data pvsqrc.ctrl >& lvs_qrc.CellName.log

Note: in the pvsqrc.ctrl I added at the end the following line

INCLUDE pvl_check.rul 

The above file contains the following lines

lvs_black_box standard_cell_name
lvs_filter_device standard_cell_name -open

So far the lvs is clean, but both layout and schematic are empty due to the black box and filtering declarations. Here's a snap shot of the summary lvs report

######################################################################################
# #
# Run Result : MATCH #
# #
# Run Summary : [WARN] Layout Netlist Is Empty #
# : [WARN] Schematic Netlist Is Empty #
# : [INFO] ERC Results: Empty #
# : [INFO] Extraction Clean #
# : [INFO] Unconnected Corresponding Top Cell Pin(s) Exists #
# ERC Summary File : myCell.sum #
# Extraction Report File : qrc_summary #
# Comparison Report File : qrc_summary.cls #
# #
######################################################################################

4. Run QRC PVS using this command

qrc -cmd ./qrc_pvs.ccl >& ./qrc.CellName.log

where in the qrc_pvs.ccl file, the following option is used as I understood from the manual that the DSPF Cell file provides the list of cells that will be exported to the DSPF netlist.

input_db -type pvs -library_cell_list_file "./dspf_cells"

Now the created dspf netlist contains only a net section with the parasitc capacitances, yet the instance section is empty.

Can you please advise what went wrong and how to get the standard cell instances to appear in the .dspf file?

Thanks a lot in advance.

Dina

Hi everyone,

I have a question regarding netlisting, matlab, spetre and the mosfet model.

From what I understand, when we run a simulation using spectre, a netlist is created which will be fed to the spectre engine. In that netlist we can find the schematic connections, simulator options and etc.

If we analyse the first part of the netlist, when it comes to the transistor definition I can see, apart from the type of transistor being used, length, width, nf, etc,  some other variables where the number of finger is used in the expression. For example, one of the variables is as, than it has an expression where the nf appears dividing a number in there.

That said, if I want to use matlab to launch the simulation, making use of the spectre/matlab toolbox, do I have to define those as well?

For example, I have tried two different situations: The first optionI have put only the basic transistor definition: Mnfet (v1 v2 0 v3) nchannel w=10e-06 l=length nf=10 and the second optionI have put exactly the same definition as before plus the other definitions (the variables) that I mentioned above that we get using spectre (where those extra variables with the number of finger dividing some numbers in the expression).

When I run the matlab script with the first option, everything goes well. But when I use in the matlab script in the second option (same definition that spectre gives me in the netlist of the same circuit), I get the following error:

Error found by spectre during circuit read-in.
    ERROR (SFE-874): "myfile.scs" 17: Unexpected equals "=".

Does anyone has an idea of what might be happening? I have a guess. Before telling what my guess is, does anyone knows what the number 17 means?

Regarding my guess: I guess that the simulator doesn't allow you to specify those extra variables, like the as mentioned above. This is something that is intrinsic to the simulator/model which it is shown in the input file that is fed to the spectre engine. I am not sure. It's just a guess.

Another experiment that I did was the following. I have ran a simple simulation using the script (with the first option configure in my script) and using spectre/ADEL simulator. For that experiment, I got different results for some capacitances, ids, gm, gmb and gds. That's why I have experiment putting in my script the same transistor definition (the extra variables with the nf dividing some number in it).

Any comments please?

Regards.

Hi, 

I'm trying to grab the data from my Spectre simulations into MATLAB using the SpectreRF Toolbox. After going through a lot of forum posts and the MatlabAN.pdf document in the toolbox folder, I think I've been able to set up all the environment variable properly. However, I'm still unable to actually execute the cds_srr() function successfully in MATLAB. I'll provide some background about the versions that I'm working with:

1. OS: CentOS 6.7 (64bit)

2. MATLAB: R2016b (64bit)

3. Spectre : 15.1.0 (32bit) (I got this info by typing in spectre -help at the terminal)

4. The MatlabAN.pdf document found in the Spectre installation folder says Product Version 6.1 June 2006. Not sure if this is an issue or not.

5. The matlab folder in the Spectre installation folder has a file cds_innersrr.mexglx and the rest are all.m files. It is my understanding that this is the 32bit version.

6. The same matlab folder listed in (5) also has a folder named 64bit. This has a file named cds_innersrr.mexa64 and the remainder are all .m files. I'm assuming this is the 64bit version (as the name suggests).

• When I set the environment variables to point to the 32bit version of the SpectreRF toolbox (listed in (5) above), and I try to execute cds_srr(), I get the following error:

Undefined function or variable 'cds_innersrr'.

Error in cds_srr (line 16)
sig = cds_innersrr(dirname);

• So I changed the environment variables to point to the 64bit version of the toolbox (listed in (6) above) and executed cds_srr(). This results in MATLAB crashing and the crash report says this at the end:

This error was detected while a MEX-file was running. If the MEX-file is not an official MathWorks function, please examine its source code for errors. Please consult the External Interfaces Guide for information on debugging MEX-files.

I'm trying to understand if it is at all possible to solve this issue without going through customer support. Is it a version issue? Any help/tips would be really helpful!

Thanks!

Hi,

I wanted to bind multiple command to single bind key.

I m trying hiSetBindKey("Schematic" " R" "hiReszieWindow(hiGetCurrentWindow() list(31:40 1323:938)) schZoomFit(1.0 0.9)")

So when i press R first part work which is resizing window. 2nd part of zoom fit doesn't work. Does someone know how to do this ?

Thanks

Hi,

When I am probing certain net in Schematic design, it keeps on flashing. Can anyone tell me how to stop it ?

Also, is there way to increase thickness of net when its probed ?

Than

Hello,

I just started designing Power converters in Cadence Virtuoso. I am trying to implement an Open loop buck converter with the following specifications:

Vin - 5V

Vout - 1.8V

Fsw - 1MHz

Iload - 5A

L - 1uH, C - 200uF

I am using TSMC 250nm PDK and simulating my design using Spectre.

How do I design the power switching device for this design? In general, how do I implement a Power FET?

Thank You!

Hi,

I am trying to implement a delay free integrator with transfer function = 1/(1-Z^-1) using the model writer of the cadence virtuoso  the corresponding generated code is mentioned below.

Problem: When an input sampled signal of 1kHz and 900 microV ( = V_peak) is applied the output of the integrator is cosine but with output magnitude from 0 to 73 mV.  Is there any problem with code or is there any special setting is required. If the input is 100 mV (= V_peak) then output of the integrator is in kVs.

Please help.

I am attaching screenshots of the schematic and transient response of the integrator (bottom is integrator output while top one is sample and hold output)

//     FUNCTION: Z-domain Filter
//      VERSION: $Revision: 2.8 $
//       AUTHOR: Cadence Design Systems, Inc.
//
// GENERATED BY: Cadence Modelwriter 2.31
//           ON: Thu Feb 02 08:59:10 IST 2017
//
// Description:  N degree Transfer functions of  H(z)
//    May be specified as a Polynomial or as Poles and Zeros.
//
//    Complex Poles and Zeros must have conjugates.
//
//
//    This model is an example, provided "as is" without express or
//    implied warranty and with no claim as to its suitability for
//    any purpose.
//
// PARAMETERS:
//   first = Delay before taking first sample [S]
//    samp = Sampling period [S]
//   trans = Transtion time [S]
//

`include "discipline.h"
`include "constants.h"

//  model ztrans



//   Z-domain in Numerator-Denominator form
//   Filter order is:  1 / 2
 
module ztrans (vin, vout);
  input vin;
  output vout;
  electrical vin, vout;
  parameter real samp = 3.90u from (0:inf);      



//               nxN  is  numerator of degree N.
//               dxN  is  denominator of degree N.
  parameter real nx0 = 1.0;
  parameter real dx0 = 1.0;
  parameter real dx1 = -1;

    analog begin
        V(vout) <+  zi_nd( V(vin), { nx0 },
                 { dx0, dx1 }, samp);
    end

endmodule

Hi,

I am working on analog circuit design using Cadence Virtuoso. The layout Suite I use is version IC6.1.6-64b.500.8

I never had any formal training on layout design. In last two years, I gathered only hands on knowledge by experimenting a lot. However, in last few months I am struggling with LVS issues which I am still unable to solve. I am requesting for any intelligent reference where I can get some help regarding the same.

Regards,

Saikat Chatterjee

Hi,

I am looking for a way to inject a voltage source (or a resistor etc.) into an existing net. My goal is to manipulate the voltage on the net, e.g. changing the threshold voltage of a MOSFET by injecting a vsource between gate an net connected to it. One solution I can think of is changing the schematic using Skill code - but I would like to avoid that. Another option is to modify the Spectre netlister, which basically works but feels too much of a hack to me.

Is there another, minimally intrusive way of achieving the same thing? E.g. some Spectre solution like alter statement or alike? Ideally I would like to create Spectre code which can be simply included into the existing and unchanged netlist. 

Thanks and best regards,

Christoph

hi

can any one guide where can i get the help documentation for "root raised cosine" filter setting and parameters (rflib >> root raised cosine filter). OR any other resource that may help to understand its parameters. 

Thanks 

Hi,

I would like to annotate the operating points of my transistors (ADE L-> Results -> Annotate -> DC Operating Points). The annotations are always the same: Id Gm_M1 Gds_M1 Gmoverid_M1 Self_gain_M1 Vgs Vds Cdd_M1 Cgg_M1 C_Csdext.

Now I know how this works: Tools -> CDF -> Edit.

However, I cannot use layer Basic because it is the devices library which is 1.) system wide 2.) I do not want to mess with. And I cannot use User Layer because it is discarded every time I restart Virtuoso.

I have also found View->Annotations->Setup in the Schematic Editor. However, it seems I it always stores the settings for the current cell or so. I do not quite understand the annotation setup. I just know that from time to time I end up entering all the annotations again and again because they are somehow lost. This is annoying.

I also ended up using CDF, exporting the whole user CDF and loading in in .cdsinit via load(). But also this caused problems and seems to be extremely fragile: It stores the whole CDF (80 kB!) although all I need is the information which information to display in the annotations.

Is there an easy, reliable way to configure the annotations globally and statically for all cells? Also, since the device library contains dozens of devices it would be great if this could be configured with a command rather than clicking through the GUI many times.

I think all I need would be to set "cdfId->opPointLabelSet" statically and globally.

Thank you!

Hi all.

I'm following the procedure depicted on https://community.cadence.com/cadence_blogs_8/b/rf/archive/2009/01/07/tip-of-the-week-how-to-simulate-a-subcircuit-netlist-with-spectre-in-ade 

My subckt declaration on the netlist matches with the pins on the symbol. 

subckt adc_sh_comparator DVDD VDDA1 VDDA2 VSS VSSA1 \
VSSA2 cfg_cmp_i\(7\) cfg_cmp_i\(6\) cfg_cmp_i\(5\) cfg_cmp_i\(4\) \
cfg_cmp_i\(3\) cfg_cmp_i\(2\) cfg_cmp_i\(1\) cfg_cmp_i\(0\) \
cmp_3v3_o en_i isnk0_i isnk1_i isnk2_i isnk_pa1_i isnk_pa2_i \
isnk_pa3_i isrc_pa1_o isrc_pa2_o isrc_pa3_o track_i vdac_i vin_i \
vout_db_o vout_o vrefp_i

I tried the procedure with another schematic and it worked.

So I suspected that I have to clean or redefine some pin order.

Thanks in advance

Hi,

I did the following:

I used the Layout XL "Generate all from source" feature to generate a layout from my schematic. The schematic i used, though did contain instances which did not have layout cells. Therefore all these instances got "flattened" in the generated layout. This was intended and the idea was to use modgens to cope with all the flattened cells and their devices in the generated layout. So far everything worked fine... XL binding established etc...

The problem i have now is that when i try to back annotate the dummies i used in the modgens i get messages like:

*WARNING* (LX-3101): Cannot create instance terminal for terminal 'S' on schematic instance 'ModgenDummy_0_75_Modgen_3' because the schematic net 'UNIT_CELL_2X_1_I/net012' does not exist in cellview 'IDAC/schematic'.

Which results in dummy instances being generated in the schematic but without net connections. This makes perfectly sense because in the schematic the original hierarchy still exists  (and the nets are in different hierarchy ) whereas in the layout the cells got flattened. Up to this point it seemed that Layout XL could keep track of this non the less...

My question is now, if there is a solution to this problem or if it was a bad idea in the beginning to have "Generate all from source" "flatten" the cells in the layout....

I thought about flattening the schematic the as well (how could i do this?), back annotate dummies and do LVS...

Any suggestions?

Thanks and best regards,

Markus

I have a mixed signal design in which I want to probe the current of several supply/gnd connections within the toplevel design.

I encounter the problem that from a number of submodules I cannot print the value of a flow probe in the simvision window when I am interactively debugging the testcase.

However the currents are visible in the wave window so these are probed and flow values can be observed.

Sofar I used the the following commands:

# Check if the node exists:

puts  [value $top.$dut.abln_common_npor4v_uvvcc4v62_1.DVCC]
4.95598

# set the flow probe for the node:

probe -create -flow $top.$dut.abln_common_npor4v_uvvcc4v62_1.DVCC

run 1 us

# Print the flow probe value

puts  [value -flow $top.$dut.abln_common_npor4v_uvvcc4v62_1.DVCC]

ncsim: *W,NOFLPR: A flow probe must exist to access the flow value.
ncsim: *W,OBANOVL: The object $top.$dut.abln_common_npor4v_uvvcc4v62_1.DVCC does not exist, so its value appears as an asterisk.

Both warnings are not correct because the node as well as the flobe probe does exist

Some pins of the block can be probed & logged but some not and it is not a problem if the port is of the inout type because some ports of this type can be printed and some not

Any idea what the cause could be?

Hi,

I am under the process of migrating my design from an older PDK version to a newer version. In the older version, whenever I used to export my schematic to netlist via the export tool, at the end of the netlist of my block i used to get empty definitions of basic blocks like nfet/pfet  coming from the pdk library. However, in the newer pdk version, these empty definitions are not there anymore.

So, whenever I run LVS using this netlist, the LVS tools complains that the source netlist references but does not define the subckt. The LVS passes the moment I add these empty definitions.

I have checked that the export netlist form is same in new and old pdk.

The old pdk is using IC6.1.6, the newer pdk is using IC 6.1.7. For LVS, Calbre is being used.

BR

alok

Hello, 

I have installed Cadence 617 that runs from a RHEL server 5.6, when I try to launch virtuoso I receive the following message. 

Make sure that cdsGetOABinPath is part of the Cadence installation

Error: No proper OA2.2 installation found. 

Any help would be great. 

Thanks

hi,

    I used to use PAS in linux and I know how to set the envoronment varibles on linux. now I have install the PAS in windows but didn't know how to set up the lic envoronment varibles and start up the license check server.  I have check all the pdf file but  none of them told me the specific way.   Could anyone tell me where to find the installation guide or just simply tell me how to configure the whole process?  

  The other question is is there guide that could inform me how to integrate thePDES10(pcell) into IC 616?  again, the soft include no guide.

thank in advance.

BR

Hi,

Yesterday a friend told me about the VEC file option for spectre. It looks great! But now I spent many hours to get a simple shift register to work but I get unreliable results. Sometimes it works, sometimes not and by just making minor changes (e.g. adding a flip flop to the register) makes completely unpredctable results. This is one of my stimulus files:

radix 1 1 4 4 4 4 4 4 1
io i i i o
vname RST LOAD D<0:3> D<4:7> D<8:11> D<12:15> D<16:23> OUT
tfall 0.01
trise 0.01
vih 1.0
vil 0.0
voh 1.0
vol 0.0
tunit 1ns
; t     RST     LOAD    D1      D2      D3      D4      D5      D6      OUT
0       1       0       F       0       0       0       0       0       x
10      0       0       F       0       0       0       0       0       x
30      1       1       F       0       0       0       0       0       x
50      1       0       F       0       0       0       0       0       x

First and most importantly, do I understand correctly that an ideal voltage source with source resistance 10mOhm is connected to all the listed nodes (e.g. D0, D1, D2, ..., D23) and are either made 1V or 0V?

How can it then come that there are nodes (D4, D5) which go into a transistor gate and are 550mV?? I tried making "outz 0.000000001" (basically zero), so no matter what the circuit does (even if it's not a gate) there is no way this node can ever be 550mV. All lines D0 - D23 go into eactly the same cell (a 1:2 MUX) and two of them are just 550mV. This makes zero sense to me!

Furthermore I get unpredictable results when I use radix 8, 16, 21, 32. So I ended up splitting them into D<0:3> D<4:7> D<8:11> D<12:15> D<16:23>. Not nice. The manual says "alid vector sizes include1 (binary), 2, 3 (octal), or 4 (hexadecimal)." which implies to me 16 or 32 or 21 would also be valid.

For example,

radix 1 1 16 1
io i i i o
vname RST LOAD D<0:15> OUT

gives the error

Error found by spectre during Digital Vector read-in.
    ERROR (USIMPRS-17704): The number of names do not match the number of vectors. Change the number of names to match the number of vectors and run the simulation again.
        
        **** Statement details for above warning or error ****
         Statement: vname RST LOAD D<0:15> OUT
         File Name: test1.vec
         Line Number: 3
        **** End of Statement details ****

But radix 8 works (which is not explicitely listed in the manual either). I would not see why 8 would work but not 16, 24 or 32.

On the other hand,

radix 1 1 111111111111111111111 1
io i i i o
vname RST LOAD D<0:20> OUT
tfall 0.01
trise 0.01
vih 1.0
vil 0.0
voh 1.0
vol 0.0
tunit 1ns
0       0       0       111111111111111111111   0

gives no error but the results make no sense (see above - 550mV although pin is only connected to a MOS gate).

Since the whole thing is so unpredicable I would like to know if this syntac is definitely valid or if it just results in unpredicted behavior without explicitely raising an error.

Any help would be greatly appreciated!

(Spectre  16.1.0.187.isr1 64bit -- 8 Dec 2016)

(a complete example that fails is hard to provide because first it includes proprietory standard cells and second it works perfectly with - say 4 flip flops - but just adding 5 messes up all results in a weird way ...)

(Using vdc and vpulse seems to work as well)