Hi,
I was wondering if there is additional documentation for the vthmod option value "maxgm", beside that in chapter 8 of the Spectre User's Manual. For example, I'd like to know how exactly the tangent is calculated at the gm maximum.
Thanks
Ignacio
Hello,
I start to work recently with Model Generator (ModGen) in Cadence Layout XL editor. The Cadence version is IC6.1.5 64 bit.
In order to interdigitate my matched array transistors with a specific pattern I need to define first the m-factor of the transistors, just an example I took this from Cadence help manual :
"......For example, if you have two devices with an m-factor of four, and you specify two rows with the base pattern of ABBA, you would create the following interdigitation pattern:
A B B A
A B B A.... "
If I don't set m then ModGen can not interdigitate my transistors.
However, there is no option I can see about Multiplication Factor (m) from the instance properties as I have attached in this image. Then from where I can set this variable?
Thank you
Regards
Hello,
I tried to import an HSPICE netlist into Cadence IC but I got an error (SPICEIN-24).
The netlist I tried to import contained multiple instances of a custom cell that is stored in the same libarary that I want to import the netlist into. For example, the netlist is something like:
****
xi net0 net1 vdd! 0 custom_cell
.end
The custom_cell is in the output library.
the error I get is:
Master cell CDF data not found for 'outputlibrary.custom_cell'
I put all the related libraries in the reference libraries in the GUI. Also, I unchecked 'Trigger CDF parameters callback'
I checked all similar posts, but none of them talked about depending on custom cells
What am I missing here?
Hello,
I am unable to find the root cause for the following error . I have created a new work space, I tired to copy the model files which has this type .scs model, it didnt resolve the issue. Is there some pdk settings I need to modify to identify this. the schematic simulates, if I delete the resistor, and have other transistors or even different metal type resistor but receives netlist error when I used this particular poly hires . Following is the error message any ideas are appreciated.
Netlist Error: Could not find netlist procedure:pdkSpectreResistor instance "R0" in cell-view
Thanks.
How to correct DRC errors.
Yahoo mail is one of the best choice of the every people for using business or personal using purpose. And we all know email is one of the best choice search engines as well as business direction over the world. Yahoo have million numbers of the yahoo mail users which is work on Email not only for sharing data but also for the multipurpose like latest news, sports astrology, finance and much more, but issues is a part of technical parts or life, so that Yahoo Mail Customer Service Number to provides best services to solves day to day glitches that users faced. We are a technical support for yahoo mail you connect with us by dialing our toll-free number 1-833-284-2444 and get resolve of every glitches at any time.
I get a new core dump each time I launch icfb (IC5141). I'm not sure why and I would like to fix it.
Here is the error message below:
\o Aborted (core dumped)
\o *Error* Failed to launch WaveScan. There is a problem with the DFII
\o installation hierarchy (Exit Code = 214).
\o For further assistance, contact Cadence Customer Support
\o with the diagnostic information available in the log file.
\o You can use AWD as your waveform viewer until the problem
\o is resolved.
\o *Info* Dumping diagnostic information ....
Here are the tool versions:
xterm> icfb -W
sub-version 5.10.41.500.6.150
xterm> spectre -W
sub-version 16.1.0.538.isr11
xterm> assura -W
sub-version 317_USR2_HF7
xterm> qrc -v
-----------------------------------------------------------------
Name : qrc - Cadence Extraction QRC - (32-bit)
Description : Parasitic Extractor
Version : 7.1.1-p006
Build Ref. No. : 443565
IR Build No. : 9358
Build Date : Thu Mar 20 01:08:43 PST 2008
-----------------------------------------------------------------
Copyright 2005 Cadence Design Systems, Inc.
Hi Team,
I have created a signal in Matlab, which is a Pseudo-Random Binary Sequence (PRBS), Then I FFT the sequence and filter the result in the frequency domain and then reverse FFT to form a time-domain sequence signal. (At this time, the sequence is no longer binary.)
I am trying to import this resulting sequence into Cadence schematic as an input signal to my analog receiver, which I designed in Cadence virtuoso.
Can anyone teach me how to do that?
Thanks
Minghao
I got this message in the log file while performing the DC simulation. Please help
error found by spectre during DC analysis `dcOp'.
ERROR (SPECTRE-16385): There were 8 attempts to find the DC solution. In some of those attempts, a signal exceeded the blowup limit of its quantity. The last signal that failed is I(I7.I4:Ttrans_flow) = -1.80144 GA, for which the quantity is `I' and the blowup limit is (1 GA). It is possible that the circuit has no DC solution. If you really want signals this large, set the `blowup' parameter of this quantity to a larger value.
ERROR (SPECTRE-16080): No DC solution found (no convergence).
Hi all,
I have a question: supposing my cell A uses a pCell B from a PDK C. I open layout of A and using express_pcell_manager I save the cache of supermaster B. I then exit the virtuoso session. Later (from the same directory I started virtuoso the last time) I restart virtuoso and open the cell A layout. Does the layout get the cached pcell informations or re-evaluate the pcell? If the cache has been saved and nothing has been changed, I assume the next session opening the layout SHOULD read the cached version. Am I wrong? Is anything to be set in the PDK, that I missed?
Hello,
I am designing a fully differential amplifier, I am using "Iprobe" to test the CMFB stability by breaking the feedback loop.
I am wondering if I want to do the layout and I don't want to remove this probe then LVS will complain, how we can make him to ignore this instance?
My Cadence version is IC6.1.5
Thank you
I am a beginner in cadence tool.
I am designing a hybrid full adder using CMOS/MTJ(magnetic tunnel junction) components. I am able to simulate the transient response clearly and obtained output for sum,carry and total power dissipation for the circuit. But while performing DC analysis (to find static power dissipation) I am getting the following errors. I have set the initial condition during the DC simulation but still the error persists.
ERROR (SPECTRE-16385): There were 8 attempts to find the DC solution. In some of those attempts, a signal exceeded the blowup limit of its quantity. The last signal that failed is I(I20.I4:Ttrans_flow) = -1.80144 GA, for which the quantity is `I' and the blowup limit is (1 GA). It is possible that the circuit has no DC solution. If you really want signals this large, set the `blowup' parameter of this quantity to a larger value.
ERROR (SPECTRE-16080): No DC solution found (no convergence).
Kindly suggest.
Thank you
Hi all,
I noticed in the last week a couple of posts about IC Design in the US were met with comments about a changing industry.
A lot of people here said that in the US a PhD is becoming a minimum requirement to do design, and people with an MS are really only able to get jobs doing validation.
Is that the case? are jobs in IC design becoming more scarce due to this high level of qualification required? are there IC design jobs that are leaving the US to China or other countries with cheaper labor?
Is it also true that its mainly the big companies that are doing IC design? I guess the constant consolidation is destroying the small firms doing IC design.
Personally I ask these questions because I'm planning in going back for my masters, and I had been considering doing microelectronics. I'm now thinking that I may be better off doing signals and communications and getting experience with FPGAs.
Hi everyone,
I don't know if it's just me or does anyone have the same problem with calculator fonts size after updating to IC6.1.7-64b.500.13?
After the new update, my calculator text size becomes really small and it's very hard to read and edit. Is there any way to fix this?
Thanks,
Dat
Hello,
I am using parametric analysis of noise simulation with three variables (L, Vdd, Vg) in the simple circuit shown below (L=60nm to 3um, 20pts), (Vdd=0 to 1, 10pts), (Vg=0 to 1, 51pts).
The parametric analysis looped on all variables correctly as shown below, but when I try to plot the thermal noise, the output family of curves are shown for the first value of L=60nm only with all combinations of Vdd and Vg.
Is there any way I can plot all curves with all variations (L, Vdd, & Vg) in Cadence Virtuoso ADE L?
I am using the following versions:
MMSIM Version: 13.1.1.660.isr18
Virtuoso Version: IC6.1.8-64b.500.1
irun Version:14.10-s039
Spectre Version: 18.1.0.421.isr9
Many thanks in advance!
How to set DC voltage parameter of "vdc" (analogLib) from the voltage generated from another instance.
For example, I have a VCVS in a schematic, which gives output X, then I want to set a DC voltage source with the same voltage X.
Thanks and Regards,
Meraj
I have a user who wants to use IC6 and spectre.
I don't see spectre with IC6 (IC 616 installed last week). On a different system, I see spectre installed in 6 other packages: EDI142, SPB166, SSV151, MMSIM141, INNOVUS151, ETS131. In InstallScape, I also see SPECTRE 171 (and 181, and 191).
Which do I need? How do I find out what I need?
Thanks,
Kyle
Hi Andrew,
I vaguely remember that there's Cadence tutorial and workshop on fractional n pll sim/verification and there's a library for it (pllLib). However, I don't recall the details and wonder if you could help point me to the path for this document?
thanks,
Kev
hello guys.
I am using IC 5.10.41.
When I used UltraSim simulator to run simulations on digital circuits, the simulation completed successfully but all the digital output voltages were 0;
I checked the log file and found the problem in the image below and I guess it is the reason why I did not get the right results.
I would appreciate it much if you can help me with this.
When using vmsUpdateCellViews for the entire library on systemVerilog views, pop-ups for the HDL parser show up stopping the command from continuing. Is there a way to overcome this?
Thanks,
Rakesh.