Dear All,
I have run a verilog module block in nc-sim.
I am able to see the input and output waveforms in SimVision.
But, I need to capture the data transition (rising edge here) time stamps of the waves into a file.
I have earlier done this using OCEAN script (cross command) for Analog circuit simulation in ADE-L/XL.
How it can be done for nc-sim simulated data.
Can anybody please tell me ?
Kind Regards,
Hello,
First post on the Cadence forums here. I'm curious if it is possible to plot RF Jitter as a result of a changing parameter (using the parametric sweep function)
I have the following expression in the "outputs" section of ADE L:
rfJitter(?result "pnoise_sample_pm0" ?unit "Second" ?from 5 ?to 2000000 ?signalLevel "rms")
However when I do a parametric sweep, I get nothing for this output.
Also is there any way to sweep parameter "m", the number of parallelized transistors?
Thanks.
I've got Monte-Carlo simulations working on very basic circuits, let's say an NMOS FET with its Gate/Drain shorted and an ideal current source pumping current into that node. My models support Monte-Carlo and I can see a gaussian distribution for Vgs across 200 samples (DC Analysis). As soon as I create a current mirror, adding a second transistor's gate to this node, the monte-carlo runs fail to complete.
Actually, the monte-carlo completes several runs successfully, then fails about 50 in a row, then completes several successfully again, and so on..
The Simulation Error Message for each of the failures reads:
ERROR (Spectre-20093): disk I/O error (error code is '10')
I can't find any additional information on what this error means. My machine has plenty of disk space and routinely handles lengthy transient sims or more difficult DC operating points.
I've tried this in both ADEXL and ADE Explorer, same error.
Virtuoso 6.1.8-64b
Spectre 18.1.0.143.isr1 64bit
Hi all,
Say I have a signal "A" with a period of "T" seconds.
I want to sample this with a period of "T" staring at "T/2" -> [T/2 3T/2 5T/2 ....]
and for the second signal, I want to sample with the same period of "T" but starting at "3T/2" (basically a delay of T) -> [3T/2 5T/2 7T/2 ....]
When I subtract these two signal I was expecting a vector subtraction (basically each column subtracted). However, that is not the case and the sampled values are subtracted based on the time they were sampled.
My question is that how can I do vector/Matrix subtraction in Cadence?
Thanks
Hi, everyone,
My cadence version is IC6.1.7 and MMSIM version is 13.1. I am using VCVS as delay unit (I know there are some delay component in analogLib like delayline, but there are some other strange phenomena).
The testbench and simulation results are shown in the following figures. The gain of vcvs is 1 and delay time is 1.1us. The vpulse period is 7ms, pulse width is 800ns as shown in fig2. The result of the first period is right as shown in fig3, but the second period result is wrong as shown in fig4. The rising and falling time of fig3 are 177ns, which changed significantly. And the fourth period is right.
Any hint on that?
Best regards,
xianweng
fig1. Testbench
fig2. configuration of vpulse
fig3. The simulation of the first period
fig4. The simulation of the second period
Dear All,
Is there way we can add a probe color of choice in schematic Editor ?
Kind Regards,
Dear All,
In Sim Vision, one can go to a particular block in Schematic Tracer also one can go to the Source Browser.
Once, it points to source browser, is it possible to create a symbol view of that portion of the code (corresponding to the block) ?
Can anybody please help me in this regard.
Kind Regards,
Hi all,
I was wondering if there are any ways to calculate DNL of a DAC in Cadene without SKILL scripting or moving data to MATLAB.
The "DNL" function in the calculator seems hard to be used and haven't been successful to use. I have also tried to use vector subtraction that didn't work as well (subtract dac output value at "i+1" and "i")
I was just wondering if there is a simple way to find the DNL in cadence.
Hello,
I am using Cadence Virtuoso IC6.1.5 64 bit.
In my design I have analog and digital parallel in-parallel out shift register. I need to fill this register with binary data.
I am using Verilog to generate my digital data bits by designing functional block and put it in my simulation test bench, then I use to run simulation and set the simulator to 'AMS'.
This configuration is not supporting all the simulations as spectra offers.
The second thing is that I need to write Verilog code every time I need different type of data.
Therefore I would like to ask you please if there is other option provided by cadence to generate pattern of parallel bits (that has configurable times and voltage) which can run under Spectra simulation
Thank you
Best Regards
Hi,
I am attempting to run a mismatch only Monte Carlo simulation on a statistical corner in ADE XL on ICADV12.3, but I get the following error:
"ERROR (ADEXL-1751): The 'Monte Carlo Sampling' run mode requires at least one corner other than statistical corners to be enabled for tests."
What I am trying to do is take my two worst case corners from a process only Monte Carlo simulation, create two statistical corners, and then run mismatch only Monte Carlo on those corners to observe the overlap. Is it not possible to run monte carlo on a statistical corner? Or do I have to dig through the weeds and create a fixed corner model file from the parameters in my worst case corner? Any information is greatly appreciated.
Cheers,
Daron
Hello
I am running noise analysis for a ramp generator. First I ran ac noise analysis (I set the operating points using actimes and ac names in tran options). Next I ran a transient noise simulation. I compared the current noise in both and they don't match (29uA in AC noise vs 60uA in transient noise). I did the same experiment for voltage noise, which seemed to match. I have attached a picture of my schematic.
Regards
Jatin
I am using 130nm process，adding my own devices，DRC is passed，but LVS got an error below： Anyone who had the same problem or know how to sovle it, please help !!! |
Greetings,
I am trying to simulate a chip using a vcd file to read the data which I need to run the simulation. When I run a dc simulation all is fine expect the inputs which are programmed using a thermocoder. Thus I want to ask if I can declare these inputs as thermodecoder in my vcd file.
thank you in advance
Dear All,
I have a test-bench (event based only) have the blocks written in verilog and VHDL.
I want to have the test-bench as schematic view. So I have drawn the test-bench in Schematic-Composer.
So, I can run it only through ADE-L + ams.
I want to know whether this way will have same simulation time as that of the run done by using nc-verilog commands in the terminal.
Can anybody please answer my query ?
Kind Regards,
Hi all,
Can someone enlighten me on how to probe voltages on the nets and currents at the pins of a block and at the pins of a mosfet transistor on an extracted view?
What do I need to do?
Best regards.
If have a couple of spectre simulation runs running in ADEXL.Now I want to get quick results from a new job. How can I priorize it such that it take the next available license without suspending the older runs?
Hi
How can I save and plot signal within DSPF extraction.
When trying to select the signal by probing the signals in the schematic I go no response.
Thanks in advance.
Hello,
I am trying to simulate inductance of a wire through Cadence layout editor and Momentum.
After setting up momentum-virtuoso, I tried to run a momentum simulation. I get Error(ADE-3036) which, as I understand, is related to running cadence in 64-bit mode. Normally, It can be fixed from the ADE L window by going to setup-enviroment-run with 64 bit binary. But, in the case of running a simulation from the momSim instead of ADE L, we do not have that option. So, the question is, if it is possible to enforce run with 64 bit binary in momSim as well. Also, if this error (ADE-3036) can be related to something different in the case of momSim. And if so, how to fix it?
My Cadence version is 6.1.7-64b and Momentum version is 13.00.
Best Regards
Khan
Hello, I am running a big simulation, creating an 80G result. So when it finishes the simulation (output log shows 100%), still the assembler interactive result shows "running". Such a "running" status would last ~ 1 hour until it shows a correct mark in assembler.
This is annoying because, during this waiting period, I can't use the calculator to analyze unless plot waveform. I have to wait for the assembler finishing.
Is it normal or is there any way to speed up such a procedure?
BR
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