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Simulation doesn't run without AMAP folder

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Hi,

I have two questions related to the same simulation.

Q1) I'm trying to run a simulation in a separate folder. I created the empty netlistFooter and netlistHeader files inside a netlist folder. The problem is that the simulator always ask for an AMAP folder. So I copied an AMAP folder from another design. I need to perform more than 2k simulations with 2k different netlists, so I can't manually create more than 2k schematics in Virtuoso. I understand that this is probably a syntax issue, but I can't see where in the netlist it is saying that is a schematic netlist.

When I copied the amap folder from another design it worked but I'm not sure if the results will be correct since the signals are mapped to a different design.

Q2) I inserted an exit() at the end of the ocean script because I have to quit ocean before performing another simulation. Ocean is saying "killed by user" and at the end saying that "fatal error ..." but the simulation is performed and the waveforms are saved. Is it expected?

I call ocean like this: "ocean -nograph -restore core.il"

Please find below one of the netlists and the ocean script.

Thank you,

Raphael

community.cadence.com/.../4667.temp.txt


How to plot value of dynamic parameter during Transient analysis

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Hello All,

Im running a simulation where i need to do a sweep of temperature during a transient analysis.
Ive created a file that gives a parametric set of values for temperature and time.
Simulation is working and the dynamic parameter is changing but i can Not plot the dynamically changing temperature parameter.
Result browser says that temperature is a constant.
Any idea on where to look for the value of the dynamic parameter and how to plot it ?

OP annotate problem with Config based sim

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hello experts,

Seems like I'm running into a corner case that (I might be confusing in earlier post so clean up a bit):

1. if I run ADE or Ocean with schematic as top, I can annotate the corresponding schematics, with both terminal Voltage and OP;

2. if I run ADE or Ocean with Config based design as top (e.g., a few sub-blocks as behavioral and/or another few as transistor level), I can only annotate terminal Voltage but no more OP ;

so is it possible to annotate OP for Config based sim?

    IC6.1.7-64b.500.21

thanks a lot,

David

Explicitely selecting dimension of signals

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Hi,

I have relatively complex expressions in my ADE L many of them result from 2-3 loops. It is very confusing on what dimension of the signal ADE is acting on and for many parts things stop working if I remove one loop.

Example: I have a transient (noise) simulation with multiple runs set to 30. On top of that I may use parametric analysis to sweep 1-2 parameter. I want that the expressions still work when I leave out the parametric sweep (or the multiple runs).

What I want is to calculate the the standarddeviations at time VAR("T0") (this is a variable from ADE L window) over the multiple runs of the noise analysis

  • When I do a parametric analysis on top of it, these standard deviations should be plotted as a function of the swept variables. Without parametric analysis, there is just one result which should be displayed in ADE L.
  • When I do not have multiple runs, then stddev(x) = x, i.e. everything should still work but now there is just no sample set for the calculating the standard deviation

Currently I have a construct like this:

dB20(stddev(((value(v("/vo2" ?result "tran") ymax(VAR("T0"))) / stddev(value(v("/vo2" ?result "tran") ymax(VAR("T0"))))) - (value(v("/vo0" ?result "tran") ymax(VAR("T0"))) / stddev(value(v("/vo0" ?result "tran") ymax(VAR("T0"))))))))

  1. Without the ymax(VAR("T0")), ADE L crashes when there is a parametric analysis. Probably because VAR("T0") is then an array as well. However, without parametric analysis this does not work any more and I would need to manually replace ymax(VAR("T0")) with VAR("T0").
  2. How do I ensure that stddev takes the standard deviation across the multiple runs of the transient noise sim AT the point T0, rather than over the time dimension or even the parameters from the parametric analysis?

Could a trapezoidal ringing be ignorable?

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Hi,

I have a question about Trapezoidal ringing.

During my oscillator simulation, a trapezoidal ringing had happened to an internal node of a three terminal resistor.

All terminals of the resistor are connected to an ideal power source (VDD, GND).

Generally, it might be undesirable since it can be regarded as a kind of simulation error,

however, in my case, since the ringing might not affect to any other circuit's operation, I am now wondering whether I can ignore the ringing.

Any advice would be helpful.

Regards,

Sangkwon

A trapezoidal ringing, but not two point shape, happened.

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Hi,
I have a question about trapezoidal ringing.
During my oscillator simulation, a trapezoidal ringing has been found through spectre.out.
However, when I checked the problematic node reported, the shape of the ringing seems like an ADC output, a quantized analog waveform, not two point shape.
Would it be a right report ?
*** The problematic node is an internal node of a three terminal resistor of ~700 ohm.
(Plus/Minus terminal is connected to GND, and the other terminal a noisy VDD)
*** The peak to peak value of the ringing is around 20 uV.
Any advice would be appreciated.
Regards,
Sangkwon

SCH1285: cannot instantiate abstracrt view as it has no symbol or scematic

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I am trying to add Adder instances for my design  using GSCLIB045. But its showing error "SCH1285: cannot instantiate abstracrt view as it has no symbol or scematic".

Can someone please help with this?

Parameters Sweep in ADE-XL results in "netl err"

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I'm trying to use ADE-XL to sweep "input voltage" for a current drivability for regulator . 

I select 'From/To' in the 'Parameterize'  and then select 'Linear @Step Type' for input voltage sweep.

ADE-XL works correctly if:

  1. I don't set any Parameters
  2. Set a single value in the Parameters

ADE-XL results in "netl err" if:

  1. I set any type of specification for the parameter.
  2. The specific error in the log is: 


\o
\o *Info* Run start for Point ID (18 1) on testbench [
\o GF130BCD_PUMP_REGULATOR:zIMSI_VPASSPMP_PUMP_4STG_4PF:1 ].
\o
\o Resetting statistical vars
\o
\o *Info* Setting parameter values ...
\o
\o Setting var period = "25n"
\o Setting var pvdd = "2.3"
\o Setting var pvpass = "5"
\o Setting temp(T) = 27
\o Setting var tr = "100p"
\o
\o *Info* Netlist Directory =
\o /home/hsjeong/simulation/GF130BCD_PUMP_REGULATOR/zIMSI_S_VPASSPMP_PUMP_4STG_4PF/adexl/results/data/Interactive.41/1/GF130BCD_PUMP_REGULATOR:zIMSI_VPASSPMP_PUMP_4STG_4PF:1/netlist
\o
\o
\o *Info* Data Directory =
\o /home/hsjeong/simulation/GF130BCD_PUMP_REGULATOR/zIMSI_S_VPASSPMP_PUMP_4STG_4PF/adexl/results/data/Interactive.41/1/GF130BCD_PUMP_REGULATOR:zIMSI_VPASSPMP_PUMP_4STG_4PF:1
\o
\o
\o *Info* Creating Netlist for Point ID (18 1)
\o
\o generate netlist...
\o Begin Incremental Netlisting Aug 1 23:21:38 2019
\o ERROR (OSSHNL-903): Failed to generate a netlist because terminal 'SUB' of instance 'MN0' in cellview
\o 'GF130BCD_PUMP_REGULATOR/zIMSI_S_VPASSPMP_PUMP_DOUBLER_5VMOS_4pF/schematic' is unbound. Do Check and Save for a schematic cellview, and for
\o other views, check and fix the design before trying to generate the netlist
\o again.
\o
\o ERROR (OSSHNL-903): Failed to generate a netlist because terminal 'B' of instance 'MN0' in cellview
\o 'GF130BCD_PUMP_REGULATOR/zIMSI_S_VPASSPMP_PUMP_DOUBLER_5VMOS_4pF/schematic' is unbound. Do Check and Save for a schematic cellview, and for
\o other views, check and fix the design before trying to generate the netlist
\o again.
\o

How to fix it? please help me.

I recently installed a new PDK.


Adding different variable values for different corners from a file into ADE-XL using SKILL

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Dear All,

I have two variables SWING and VCM as Global Variables in my ADE-XL.

I have another variable FCLK which takes value 17G, 13G. In other words it is swept for each corner with the three values.

I have 2 corners TT and FF in my corner setup.

I have captured the SWING and VCM information in a file as below:-

###############################

corner,   FCLK, SWING, VCM 

TT,          13G,      1.3,       0.65

TT,          17G,      1.2,       0.60  

FF,          13G,      1.4,       0.7

FF,          17G,      1.3,       0.65  

###############################

Is there way we can make ADE-XL to take the appropriate value for each FCLK  sweep and the corner instead of manually adding the variables ? 

I think a SKILL script can do this. But I am not able to make it work for ADE-XL.

Can anybody please tell me how it can be done ?

Kind Regards,

can't edit value of CDF parameters in Edit Object Property form

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Hi 

I have a capacitance symbol and I need to edit  the capacitance value of that symbol.  I do "q" to bring up the Edit Object Property form and try to enter the value. 

However, I can't edit any value in that form. What would be the potential problem here ? how I can enable editable for those CDF parameters ? 

thanks 

Nhumai 

deepprobe not working for extracted cellview in ADE-XL run.

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Dear All,

I am using  deepprobe to measure the voltage of a net that is 1 hierarchy down in the PEX .spf file.

In the .spf file I have, the following line:-

R221_1 Xbuf<0>/MMNINP:G clkout_0:218 129.365.

The extracted cellView name is clkdiv.

In, the schematic viewer I have added a deepprobe with net name Xbuf\<0\>\/MMNINP\:G.

But, it is NOT probing the voltage. I see the following warning in output.log file.

WARNING (SFE-411): "input.scs" 391: Hierarchical node `clkdiv.XI221<0>/MMNINM\:G' does not exist in design. It will be treated as a regular (non-hierarchical) node.
WARNING (SFE-411): "input.scs" 392: Hierarchical node `clkdiv.XI221<0>/MMNINP\:G' does not exist in design. It will be treated as a regular (non-hierarchical) node.

Could anybody please tell, why it is happening like this and how to fix this ?

Kind Regards,

How can i enable annotations in virtuoso?

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I tried to edit the cdf to add parameters in the specific device but i am still not seeing the output of the annotations.

I will appreciate if anybody can assist with this/

Thanks

Stability analysis of a fully differential ring oscillator

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Hi, 

I'm trying to verify Barchausen criteria for a 4 stage differential ring oscillator and I'm trying to understand the different results I'm getting from stb to pss+pstb using shooting-newton/HB (With diffstbprobe from the analogLib). 

Running stb analysis:

As I saw in your workshop (/tools/spectre/examples/SpectreRF_workshop/PSTB.pdf) I should get gain>1 when phase=0.

Is it correct also for differential ring oscillator analysis?

In my analysis the phase doesn't get to 0 at the relevant frequency range.

Running pss+pstb using Shooting-Newton:

Barchausen criteria is met - gain=1 when phase=0.

DC phase is 180 as expected.

Running pss+pstb using HB I'm getting a totally different results:

DC phase is 0. Phase=~60deg when gain=1

 

What can be the reason for the different results?

Thanks,

Moran

Annotation not working even after selecting the cdsparams

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Hi,

I am currently trying to use annotations for a sample inverter but it doesn't seem to be working for the transistors. The parameters in the dc annotation menu are selected but no information is displayed on the schematic view. What do I need to do to see the parameters on the schematic. Everything looks good but it seems I am missing something important. I attached the image for further clarifications.

I am using IC6.1.7-64b.

Thanks

 

Error coming up when trying to do DRC and Extraction in CADENCE with AMS design kit

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The following are the DRC and Extraction errors coming up:

DRC started at Mon Aug 5 19:17:07 2019

Validating hierarchy instantiation for:

library: 035_Layout_PMOS_with_pads_flat_final

cell: PIOTA_TOTAL_in_padframe

view: layout

Rules come from library TECH_C35B4.

Rules path is drc.rul.

Inclusion limit is set to 1000.

Parsing drcExtractRules of "/home/ahtitus/AMS035DK/AMS_410_ISR15/cds/HK_C35/TECH_C35B4/drc.rul"...

*Error* eval: undefined function - avGetAssuraVersion

Errors exist in the rules file "/home/ahtitus/AMS035DK/AMS_410_ISR15/cds/HK_C35/TECH_C35B4/drc.rul".

Verification program terminated.

Extraction started at Mon Aug 5 19:59:04 2019

Validating hierarchy instantiation for:

library: 035_Layout_PMOS_with_pads_flat_final

cell: PIOTA_TOTAL_in_padframe

view: layout

Rules come from library TECH_C35B4.

Rules path is extract.rul.

Inclusion limit is set to 1000.

Parsing drcExtractRules of "/home/ahtitus/AMS035DK/AMS_410_ISR15/cds/HK_C35/TECH_C35B4/extract.rul"...

*Error* eval: undefined function - avGetAssuraVersion

Errors exist in the rules file "/home/ahtitus/AMS035DK/AMS_410_ISR15/cds/HK_C35/TECH_C35B4/extract.rul".

Verification program terminated.

We have imported a GSD2 file into CADENCE and was trying to run Extraction and DRC for that layout imported from the GDS2 file. We had installed a design kit custom made for CADENCE from AMS foundry. But we are facing this  undefined function - avGetAssuraVersion problem. I can see this function avGetAssuraVersion in the drc.rul file extract.rul file. Should I just comment it out. The portion where this function comes is copied below:

no_layer_DEVDEF_opto_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "no_layer_DEVDEF_opto") then no_layer_DEVDEF_opto_Q=t ))

no_layer_FIDEF_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "no_layer_FIDEF") then no_layer_FIDEF_Q=t ))

no_layer_HRES_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "no_layer_HRES") then no_layer_HRES_Q=t ))

no_layer_HVDEF_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "no_layer_HVDEF") then no_layer_HVDEF_Q=t ))

no_layer_LVTDEF_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "no_layer_LVTDEF") then no_layer_LVTDEF_Q=t ))

no_layer_MET4_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "no_layer_MET4") then no_layer_MET4_Q=t ))

no_layer_METCAP_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "no_layer_METCAP") then no_layer_METCAP_Q=t ))

no_layer_METRES_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "no_layer_METRES") then no_layer_METRES_Q=t ))

no_layer_MIDOX_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "no_layer_MIDOX") then no_layer_MIDOX_Q=t ))

no_layer_PFIMP_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "no_layer_PFIMP") then no_layer_PFIMP_Q=t ))

no_layer_POLY2_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "no_layer_POLY2") then no_layer_POLY2_Q=t ))

layer_PPLUS_DPL_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "layer_PPLUS_DPL") then layer_PPLUS_DPL_Q=t ))

no_layer_VIA3_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "no_layer_VIA3") then no_layer_VIA3_Q=t ))

no_library_PRIMLIBRF_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "no_library_PRIMLIBRF") then no_library_PRIMLIBRF_Q=t ))

no_library_SPIRALS_3M_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "no_library_SPIRALS_3M") then no_library_SPIRALS_3M_Q=t ))

no_library_SPIRALS_4M_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "no_library_SPIRALS_4M") then no_library_SPIRALS_4M_Q=t ))

no_library_SPIRALSD_4M_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "no_library_SPIRALSD_4M") then no_library_SPIRALSD_4M_Q=t ))

element_PHDNWA850_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "element_PHDNWA850") then element_PHDNWA850_Q=t ))

element_PHDNWB850_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "element_PHDNWB850") then element_PHDNWB850_Q=t ))

element_RPOLYZ_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "element_RPOLYZ") then element_RPOLYZ_Q=t ))

element_SBD5_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "element_SBD5") then element_SBD5_Q=t ))

library_ESDLIB_WIP_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "library_ESDLIB_WIP") then library_ESDLIB_WIP_Q=t ))

library_PRIMLIB_WIP_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "library_PRIMLIB_WIP") then library_PRIMLIB_WIP_Q=t ))

library_PRIMLIB_AS39513_Q=nil
if( strcmp(avGetAssuraVersion() "3.1") > 0 then
if( avHiddenSwitch( "library_PRIMLIB_AS39513") then library_PRIMLIB_AS39513_Q=t ))

;;=====================================================================

Kindly guide as to what to do???


VIVA: possible to change thickness of gridlines?

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Hi! I'd like to increase the thickness of gridlines in VIVA so that they are very visible in my screenshots. I searched the documentation but found nothing. Is there a way to tweak this?

Thanks and regards,

Jorge.

Maestro MTS-Option - how to set different reltol for different subckts?

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I came across a convergence issue and was looking for a possibility in maestro GUI to set reltol for different subckts.

In the MTS-Options of Maestro I could not find it. Therefore, I tried to work around via a Pre-Run Script (which failed), because reltol should somehow be set after netlist creation.

https://community.cadence.com/cadence_blogs_8/b/cic/posts/spectre-tech-tips-spectre-local-options

Where I can find this option in maestro, if it is available there - or how to set reltol for subckts in maestro?

Thank you in advance,

Sergej

ASSEMBLER: possible to export tests as ADE-L states?

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Hi! In ADE-XL one can right-click on a test and "save" an ADE-L state from it. In ASSEMBLER this option seems gone... is it possible to achieve this somehow? I'd like to export my ASSEMBLER test to ADE-L for debugging purposes (the simulator is ignoring the "save=selected" option and is saving all voltage nodes across the whole hierarchy!!!).

Thanks and regards, Jorge.

Layout XL - switch drain and source of a transistor with multiple fingers

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Hello community

I have transistors with 8 fingers, resulting in 4 diffusion areas for the source and 5 areas for the drain.

I'm looking for the option in Layout XL where I can switch drain and source of a transistor, leading to a layout with 5 diffusion areas for the source and 4 for the drain.

I now that I can simply connect them in a 'wrong' way and the software automatically switches the nets then. However, sometimes this does not work. I guess it's due to fixed net names?

Is there a way to manually change it?

Thanks for any advice!

Regards domi

load annotation setup

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Hi,

I saved the annotation setup using the GUI "Annotation Setup" -> Save.

Sometimes when I try to load the annotationSetup.as file, the file is not visible in the dialog box. I can see the file using unix terminal, but can't load it from GUI.

If it gets loaded, sometimes only some mos have the annotation data - the setup does not take effect of some of them. Then you have to reapply.

Depending upon pdk, vsat_marg is +ve or -ve when the pmos is in strong inversion. Can't rely on it totally.

Rgds

Bhavin

sub-version  IC6.1.7-64b.500.17

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