Hi,

When we are using vpwl voltage source in cadence test benches, we can create a particular waveform by providing voltage versus time information. Let us say, we want to repeat the same voltage waveform periodically over time, then with the SPICE command, we can do so by using the below command. The "R" option will enable the vpwl voltage source to be repeated after every 1us. 

vread<0>  read<0>    0 pwl(0 0,1u 0,2025n    0,2025.2n  1,2075n     1,2075.2n    0,2125n    0,2125.2n  1,2175n    1,2175.2n  0,3u 0,R 1u)

Simillarly, how to make a pwl wvaeform repeatative by using cadence vpwl voltage source form,

Thanks

Dear All,

There is deepprobe to find the node potential at the TestBench level while doing PEX simulation.

Is there any way to check the DC operating condition of a MOS during extracted netlist simulation ?

Kind Regards,

If I copy a pin, then new pin is always weakly connected to the original one.

Is there a way to copy a pin so that the new pin is strongly connected with the original one?

Hello,

I am using the ideal_balun for the first time to simulate the fully differential amplifier, I found no problem to convert the ground-referenced signal to fully differential signals. But when I put the balun at the output of fully differential signal to convert it to single then I find an error during the simulation and the spectra terminates.

I attached a basic simulation setup with the error message

Thank you for your help in advance   

hello experts,

it was working really well until I'm at LVS stage. I created a wrapper cell with multiplier defined like bellow:

cdfCreateParam( cdfId
    ?name "m"
   ?prompt "Multiplier"
   ?type "string"

   ?defValue "1"
   ?storeDefault "yes"
   ?parseAsNumber "yes"
   ?parseAsCEL "yes"
)

the simulator can accept that and interpenetrate, layout generator can use that and generate multiple instances of that device accordingly. but when I run LVS (sorry Calibre though), it doesn't seem to understand the schematic is asking for multiple of them so it complains why layout side has so many devices missing at schematic side.

anything I could make LVS understand this Multiplier?

thanks,

David

Hi, everyone, I have a question in the simulation of Hspice.

For the target INV cell, when I add the less input load and output load, the simulation is correct. However, when I add the more input and output load, the simulation time is so fast, and there is no ".tr0" and ".mt0" file. The print content is "hspice conclude". If I reduce the number of the load, the simulation will become correct.

Did anyone met the same case? 

The version is H-2013.03-SP1. Any suggestion will be great, thanks everyone.

Hi,

For the moment I am using ADE Assembler together with the MATLAB Integration Tools. Though, I wanted to load the results of the simulation in MATLAB in a parallel way. Is this possible?

E.g. I want to do something like this in MATLAB:

parfor dataPoint = 1:amountOfSweeps

       adeInfo.loadResult('test', 'TRANSIENT', 'DataPoint', dataPoint);

end

Or is there another way of quickly loading the results in MATLAB of, for example, 20 sweeps? Because running the code of above takes some time (especially if the amount of sweeps are larger).

Kind regards,

Nicolas

Hi there,

I have experienced a PSS convergence issue and needed some advice.

My circuit is a PLL that requires a certain time to settle, and I wanted to simulate the close-loop performance of the PLL.

I do PSS simulation, with "Run Transient" set to "Yes". Then I specify the proper time for the PLL to settle and I also saved the transient results.

The problem comes with the stop time setting. I know that the circuit will settle within 3us, verified by transient simulation, and I specify the stop time to be longer than that, for instance 4us.

What I noticed is that as I change the stop time, althoughalways longer than setting time, sometimes PSS converges and sometimes it does not.

For instance, I set 4us stop time, simulator converges and simulation finishes with expected results. Now I increase the stop time a bit longer to 4.1 us, then pss fails to converge. If I increase the stop time to 4.3us, it converges, and with 4.5us, it fails again.

The circuit is already settled at 4us, pss converges, and the results are as expected. What I don't understand is why the simulator can't converge at 4.1us.

What I noticed is that when it converges, it converges pretty fast, with just a few tries. when it fails, it also fails very fast, within a few iterations, "Conv norm" goes to very large number.

I wonder what could I do to improve this situation. I used default PSS convergence and accuracy settings, and I am using ic213_isr22 

Thanks!

Dear Team,

My computer: IC617.722 CPU: Intel Core-I7 4790 @ 3.6GHz includes 4 cores & 8 threads.

When I changed numbers of APS multi-threading to 2-8, then the simulation cannot be done. If I disable muti-threading, then it will become normal. Here are the logs,

irun(64): 15.20-p001: (c) Copyright 1995-2016 Cadence Design Systems, Inc.
TOOL: irun(64) 15.20-p001: Started on Sep 11, 2019 at 04:46:51 CST
irun
-f irunArgs
-UNBUFFERED
-cdslib ./cds.lib
-errormax 50
-status
-nowarn DLNOHV
-nowarn DLCLAP
-v93
-incdir /home/jiangn/ic_projects/adc_tislope_smic55/
-ade
-timescale 1ns/1ns
-vtimescale 1ns/1ns
-delay_mode None
-novitalaccl
-access r
-noparamerr
-amspartinfo ../psf/partition.info
-rnm_partinfo
-modelincdir /home/jiangn/ic_projects/adc_tislope_smic55/
./spiceModels.scs
./amsControlSpectre.scs
-input ./probe.tcl
-run
-exit
-ncsimargs "+amsrawdir ../psf"
-simcompatible_ams spectre
-name adc_tislope_0420_smic55_sim.8channel_top_t_ramp:config
-allowredefinition
-amsbind
-top adc_tislope_0420_smic55_sim.8channel_top_t_ramp:schematic
-top cds_globals
./netlist.vams
/home/jiangn/ic_projects/adc_tislope_smic55/adc_tislope_0420_smic55_sim/ConnRules_1V2_full_fast/connect/verilog.vams
./ie_card.scs
-f ./textInputs
-amscompilefile "file:/home/jiangn/ic_projects/adc_tislope_smic55/adc_tislope_0420_smic55/dac_12bit_ideal/veriloga/veriloga.va ftype:va lib:adc_tislope_0420_smic55 cell:dac_12bit_ideal view:veriloga"
-amscompilefile "file:/home/jiangn/ic_projects/adc_tislope_smic55/adc_tislope_0420_smic55/counter/functional/verilog.v lib:adc_tislope_0420_smic55 cell:counter view:functional"
-amscompilefile "file:/home/jiangn/ic_projects/adc_tislope_smic55/adc_tislope_0420_smic55/top_mux/functional/verilog.v lib:adc_tislope_0420_smic55 cell:top_mux view:functional"
-amscompilefile "file:/home/jiangn/ic_projects/adc_tislope_smic55/adc_tislope_0420_smic55/data_mux/functional/verilog.v lib:adc_tislope_0420_smic55 cell:data_mux view:functional"
-amscompilefile "file:/home/jiangn/ic_projects/adc_tislope_smic55/adc_tislope_0420_smic55/register_d2/functional/verilog.v lib:adc_tislope_0420_smic55 cell:register_d2 view:functional"
-amscompilefile "file:/home/jiangn/ic_projects/adc_tislope_smic55/adc_tislope_0420_smic55/register_d1/functional/verilog.v lib:adc_tislope_0420_smic55 cell:register_d1 view:functional"
-amscompilefile "file:/home/jiangn/ic_projects/adc_tislope_smic55/adc_tislope_0420_smic55/register_stg/functional/verilog.v lib:adc_tislope_0420_smic55 cell:register_stg view:functional"
-makelib adc_tislope_0420_smic55_sim
-endlib
./cds_globals.vams
-l ../psf/irun.log
-spectre_args ++aps
-spectre_args +mt=4
file: /home/jiangn/ic_projects/adc_tislope_smic55/adc_tislope_0420_smic55/register_stg/functional/verilog.v
ncvlog: *W,SPDUSD: Include directory /home/jiangn/ic_projects/adc_tislope_smic55/ given but not used.
Total errors/warnings found outside modules and primitives:
errors: 0, warnings: 1
ncvlog: Memory Usage - 20.6M program + 30.3M data = 51.0M total
ncvlog: CPU Usage - 0.0s system + 0.0s user = 0.0s total (0.3s, 9.3% cpu)
Caching library 'adc_tislope_0420_smic55' ....... Done
Caching library 'adc_tislope_0420_smic55_sim' ....... Done
Caching library 'worklib' ....... Done
Elaborating the design hierarchy:
Top level design units:
8channel_top_t_ramp
cds_globals
Discipline resolution Pass...
Doing auto-insertion of connection elements...
Connect Rules applied are:
logic_cr
Building instance overlay tables: .................... Done
Building instance specific data structures.
Loading native compiled code: .................... Done
Design hierarchy summary:
Instances Unique
Modules: 175 39
Registers: 237 132
Scalar wires: 62 -
Expanded wires: 12 1
Vectored wires: 64 -
Always blocks: 183 60
Initial blocks: 31 24
Cont. assignments: 31 21
Pseudo assignments: 8 8
Interconnect: 370 -
Simulation timescale: 1ps
Writing initial simulation snapshot: adc_tislope_0420_smic55_sim.8channel_top_t_ramp:config
ncelab: Memory Usage - 49.0M program + 55.8M data = 104.9M total (Peak 238.9M)
ncelab: CPU Usage - 0.1s system + 0.1s user = 0.2s total (0.6s, 35.3% cpu)
Loading snapshot adc_tislope_0420_smic55_sim.\8channel_top_t_ramp :config .................... Done
Simulating in AMS-SIE mode...
Starting analog simulation engine...
AMSD: Using spectre solver with arguments: ++aps +mt=4.

Cadence (R) Virtuoso (R) Spectre (R) Circuit Simulator
Version 15.1.0.284.isr1 64bit -- 10 Dec 2015
Copyright (C) 1989-2015 Cadence Design Systems, Inc. All rights reserved
worldwide. Cadence, Virtuoso and Spectre are registered trademarks of
Cadence Design Systems, Inc. All others are the property of their
respective holders.

Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA
Security, Inc.

User: jiangn Host: server HostID: 7F0101 PID: 21196
Memory available: 1.9603 GB physical: 16.7045 GB
Linux : Ubuntu 18.04.3 LTS
CPU Type: Intel(R) Core(TM) i7-4790 CPU @ 3.60GHz
All processors running at 3791.3 MHz
Socket: Processors (Hyperthreaded Processor)
0: 0 ( 4 ), 1 ( 5 ), 2 ( 6 ), 3 ( 7 )

System load averages (1min, 5min, 15min) : 55.0 %, 52.1 %, 55.5 %
Hyperthreading is enabled

Analog Kernel using -ANALOGCONTROL ./spiceModels.scs.
Reading file:
/home/jiangn/simulation/8channel_top_t_ramp/ams/config/netlist/spiceModels.scs
Reading file:
/home/jiangn/simulation/8channel_top_t_ramp/ams/config/netlist/netlist.vams
Reading link: /cadtools/cadence/INCISIVE152/tools
Reading file:
/cadtools/cadence/INCISIVE152/tools.lnx86/affirma_ams/etc/connect_lib/E2L_2.vams
Opening directory spiceModels.ahdlSimDB/ (775)
Opening directory
spiceModels.ahdlSimDB//2728_tools_affirma_ams_etc_connect_lib_E2L_2.vams.connectLib__E2L_2__module__0x10000001_behavioral.ahdlcmi/
(775)
Opening directory
spiceModels.ahdlSimDB//2728_tools_affirma_ams_etc_connect_lib_E2L_2.vams.connectLib__E2L_2__module__0x10000001_behavioral.ahdlcmi/Linux-64/
(775)
Reading file:
/home/jiangn/simulation/8channel_top_t_ramp/ams/config/netlist/spiceModels.ahdlSimDB/2728_tools_affirma_ams_etc_connect_lib_E2L_2.vams.connectLib__E2L_2__module__0x10000001_behavioral.ahdlcmi/Linux-64/obj/optimize/5.0/libahdlcmi_connectLib__E2L_2__module__0x10000001_behavioral.so
Installed compiled interface for
connectLib__E2L_2__module__0x10000001_behavioral.
Reading file:
/cadtools/cadence/INCISIVE152/tools.lnx86/affirma_ams/etc/connect_lib/L2E_2.vams
Opening directory spiceModels.ahdlSimDB/ (775)
Opening directory
spiceModels.ahdlSimDB//2728_tools_affirma_ams_etc_connect_lib_L2E_2.vams.connectLib__L2E_2__module__0x10000001_behavioral.ahdlcmi/
(775)
Opening directory
spiceModels.ahdlSimDB//2728_tools_affirma_ams_etc_connect_lib_L2E_2.vams.connectLib__L2E_2__module__0x10000001_behavioral.ahdlcmi/Linux-64/
(775)
Reading file:
/home/jiangn/simulation/8channel_top_t_ramp/ams/config/netlist/spiceModels.ahdlSimDB/2728_tools_affirma_ams_etc_connect_lib_L2E_2.vams.connectLib__L2E_2__module__0x10000001_behavioral.ahdlcmi/Linux-64/obj/optimize/5.0/libahdlcmi_connectLib__L2E_2__module__0x10000001_behavioral.so
Installed compiled interface for
connectLib__L2E_2__module__0x10000001_behavioral.
Reading file:
/home/jiangn/simulation/8channel_top_t_ramp/ams/config/netlist/cds_globals.vams
Reading file:
/home/jiangn/simulation/8channel_top_t_ramp/ams/config/netlist/INCA_libs/AMSD/ahdl_in/ahdlIncludes.scs
Reading file:
/home/jiangn/ic_projects/adc_tislope_smic55/adc_tislope_0420_smic55/dac_12bit_ideal/veriloga/veriloga.va
Reading link:
/cadtools/cadence/INCISIVE152/tools.lnx86/spectre/etc/ahdl/constants.h
Reading file:
/cadtools/cadence/INCISIVE152/tools.lnx86/spectre/etc/ahdl/constants.vams
Reading link:
/cadtools/cadence/INCISIVE152/tools.lnx86/spectre/etc/ahdl/discipline.h
Reading file:
/cadtools/cadence/INCISIVE152/tools.lnx86/spectre/etc/ahdl/disciplines.vams
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/l0055ll_v1p3_1r_spe.lib
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/l0055ll_v1p3_1r_mis_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/l0055ll_v1p3_1r_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/l0055ll_v1p3_1r_ldmos_spe.ckt
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/l0055ll_v1p3_1r_bjt_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/pnp12a100ll_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/pnp12a25ll_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/pnp12a4ll_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/pnp18a100ll_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/pnp18a25ll_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/pnp18a4ll_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/pnp25a100ll_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/pnp25a25ll_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/pnp25a4ll_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/npn12a100ll_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/npn12a25ll_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/npn12a4ll_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/npn18a100ll_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/npn18a25ll_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/npn18a4ll_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/npn25a100ll_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/npn25a25ll_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/npn25a4ll_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/pnp12a100ll_sh_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/pnp12a25ll_sh_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/pnp12a4ll_sh_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/pnp18a100ll_sh_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/pnp18a25ll_sh_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/pnp18a4ll_sh_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/pnp25a100ll_sh_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/pnp25a25ll_sh_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/pnp25a4ll_sh_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/npn12a100ll_sh_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/npn12a25ll_sh_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/npn12a4ll_sh_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/npn18a100ll_sh_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/npn18a25ll_sh_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/npn18a4ll_sh_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/npn25a100ll_sh_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/npn25a25ll_sh_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/bjt/npn25a4ll_sh_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/l0055ll_v1p3_1r_dio_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/l0055ll_v1p3_1r_res_spe.ckt
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/res.va
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/l0055ll_v1p3_1r_res_spe.mdl
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/l0055ll_v1p3_1r_var_spe.ckt
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/gc.va
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/l0055ll_v1p3_1r_mom_spe.ckt
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/ms0055ll_io25_rf_v1p3_2r_spe.lib
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/ms0055ll_io25_rf_v1p3_2r_spe.ckt
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/ms0055ll_io25_rf_v1p3_2r_mis_spe.ckt
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/ms0055ll_io25_rf_res_v1p3_2r_spe.ckt
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/res_rf.va
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/ms0055ll_io25_rf_var_v1p3_2r_spe.ckt
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/gc_rf.va
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/ms0055ll_io25_rf_mom_v1p3_2r_spe.ckt
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/ms055_rf_1tm_spe_v1p3_2r.ckt
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/ms055_rf_1tm_psub_spe_v1p3_2r.ckt
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/ms055_diff_1tm_spe_v1p3_2r.ckt
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/ms055_diff_1tm_psub_spe_v1p3_2r.ckt
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/ms055_rf_1talpa_spe_v1p3_2r.ckt
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/ms055_rf_1talpa_psub_spe_v1p3_2r.ckt
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/ms055_rf_diff_1talpa_spe_v1p3_2r.ckt
Reading file:
/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/models/spectre/ms055_rf_diff_1talpa_psub_spe_v1p3_2r.ckt
Reading file:
/home/jiangn/simulation/8channel_top_t_ramp/ams/config/netlist/amsControlSpectre.scs
Reading file:
/home/jiangn/simulation/8channel_top_t_ramp/ams/config/netlist/ie_card.scs
Reading file:
/home/jiangn/simulation/8channel_top_t_ramp/ams/config/netlist/.amsbind.scs
Reading file:
/cadtools/cadence/INCISIVE152/tools.lnx86/spectre/etc/configs/spectre.cfg
Time for NDB Parsing: CPU = 522.851 ms, elapsed = 632.272 ms.
Time accumulated: CPU = 695.133 ms, elapsed = 632.275 ms.
Peak resident memory used = 129 Mbytes.

ncsim> source /cadtools/cadence/INCISIVE152/tools/inca/files/ncsimrc
ncsim>
ncsim> # This is the NC-SIM(R) probe command file
ncsim> # used in the AMS-ADE integration.
ncsim>
ncsim>
ncsim> #
ncsim> # Database settings
ncsim> #
ncsim> if { [info exists ::env(AMS_RESULTS_DIR) ] } { set AMS_RESULTS_DIR $env(AMS_RESULTS_DIR)} else {set AMS_RESULTS_DIR "../psf"}
../psf
ncsim> database -open ams_database -into ${AMS_RESULTS_DIR} -default
Created default SHM database ams_database
ncsim>
ncsim> #
ncsim> # Probe settings
ncsim> #
ncsim> probe -create -emptyok -database ams_database -all -depth all {\8channel_top_t_ramp }
Created probe 1
ncsim> probe -create -emptyok -database ams_database -all cds_globals
Created probe 2
ncsim> probe -create -emptyok -database ams_database -aicms -all -depth all {\8channel_top_t_ramp }
Created probe 3
ncsim>
ncsim> run

The CPU load for active processors is :
Spectre 0 (88.2 %) 1 (86.0 %) 2 (75.5 %) 3 (100.0 %)
4 (14.3 %) 5 (51.1 %) 6 (59.1 %) 7 (16.1 %)
Other

Warning from spectre during circuit read-in.
WARNING (SFE-2654): VerilogA module `aigg_hdl' override primitive/(verilogA
module) `aigg_hdl'.

Existing shared object for module dac_12bit_ideal is up to date.
Installed compiled interface for
adc_tislope_0420_smic55__dac_12bit_ideal__veriloga.

Warning from spectre in `cds_globals', during circuit read-in.
WARNING (SFE-2946):
"/home/jiangn/simulation/8channel_top_t_ramp/ams/config/netlist/cds_globals.vams"
21: `cds_globals': Parameter `VDD' redefines parameter of same name
defined at higher level. Local parameter value will be used.
WARNING (SFE-2946):
"/home/jiangn/simulation/8channel_top_t_ramp/ams/config/netlist/cds_globals.vams"
22: `cds_globals': Parameter `d' redefines parameter of same name
defined at higher level. Local parameter value will be used.
Warning from spectre during hierarchy flattening.
WARNING (SFE-884):
"/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/smic55llrf/../models/spectre/l0055ll_v1p3_1r_spe.lib"
26: The option 'gmin' is deleted because it is redefined at
'amsControlSpectre.scs':line '9'.
WARNING (SFE-884):
"/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/smic55llrf/../models/spectre/l0055ll_v1p3_1r_spe.lib"
26: The option 'scale' is deleted because it is redefined at
'amsControlSpectre.scs':line '9'.
WARNING (SFE-884):
"/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/smic55llrf/../models/spectre/l0055ll_v1p3_1r_spe.lib"
8635: The option 'scale' is deleted because it is redefined at
'amsControlSpectre.scs':line '9'.
WARNING (SFE-884):
"/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/smic55llrf/../models/spectre/l0055ll_v1p3_1r_spe.lib"
6637: The option 'scale' is deleted because it is redefined at
'amsControlSpectre.scs':line '9'.
WARNING (SFE-884):
"/eda/pdk/smic55/pdk/smic55llrf_1tm_9k_oa_1P9M_2012_7_17_v1.3/smic55llrf/../models/spectre/l0055ll_v1p3_1r_spe.lib"
4714: The option 'scale' is deleted because it is redefined at
'amsControlSpectre.scs':line '9'.
Further occurrences of this warning will be suppressed.

The simulator has reused the existing Verilog-A libraries for this simulation
run. If you do not want to use these libraries, set the
'CDS_AHDL_REUSE_LIB' environment variable to 'NO' and rerun the
simulation.
Reusing Verilog-A library
/home/jiangn/simulation/8channel_top_t_ramp/spectre/schematic/netlist/input.ahdlSimDB/bsource_0825ce.va.bsource_0825ce.ahdlcmi/Linux-64/obj/optimize/5.0/libahdlcmi_bsource_0825ce.so.
Existing shared object for module bsource_0825ce is up to date.
Installed compiled interface for bsource_0825ce.
Time for Elaboration: CPU = 230.144 ms, elapsed = 362.053 ms.
Time accumulated: CPU = 925.379 ms, elapsed = 994.427 ms.
Peak resident memory used = 164 Mbytes.

Time for EDB Visiting: CPU = 18.141 ms, elapsed = 18.153 ms.
Time accumulated: CPU = 943.689 ms, elapsed = 1.01275 s.
Peak resident memory used = 167 Mbytes.

Notice from spectre during topology check.
Only one connection to the following 4 nodes:
GND!
VDD!
VSS!
8channel_top_t_ramp.vout
Warning from spectre during initial setup.
WARNING (SPECTRE-294): Too many saved signals [ 1221 ]. Slow initialization
is expected!

Global user options:
addflowsuffix = yes
dotprobefmt = hier
scale = 0.9
scale = 0.9
scale = 0.9
scale = 0.9
scale = 0.9
scale = 0.9
scale = 0.9
scale = 0.9
scale = 0.9
temp = 27
tnom = 27
scale = 1
scalem = 1
reltol = 0.001
vabstol = 1e-06
iabstol = 1e-12
gmin = 1e-12
rforce = 1
maxnotes = 5
maxwarns = 5
digits = 5
pivrel = 0.001
checklimitdest = psf
rawfmt = sst2
save = selected

Scoped user options:

Circuit inventory:
nodes 503
adc_tislope_0420_smic55__dac_12bit_ideal__veriloga_behavioral 1
bsim4 608
bsource_0825ce 44
connectLib__E2L_2__module__0x10000001_behavioral 19
connectLib__L2E_2__module__0x10000001_behavioral 12
isource 16
vsource 18

Analysis and control statement inventory:
info 4
tran 1

Output statements:
.probe 0
.measure 0
save 1265

Notice from spectre during initial setup.
Fast APS Enabled.
6 warnings suppressed.
Multithreading Enabled: 4 threads in the system with 8 available
processors.

Time for parsing: CPU = 135.363 ms, elapsed = 203.052 ms.
Time accumulated: CPU = 1.07921 s, elapsed = 1.21596 s.
Peak resident memory used = 174 Mbytes.

~~~~~~~~~~~~~~~~~~~~~~
Pre-Simulation Summary
~~~~~~~~~~~~~~~~~~~~~~
~~~~~~~~~~~~~~~~~~~~~~

**************************************************
Transient Analysis `tran': time = (0 s -> 22.4 us)
**************************************************

Notice from spectre during IC analysis, during transient analysis `tran'.
Bad pivoting is found during DC analysis. Option dc_pivot_check=yes is
recommended for possible improvement of convergence.

DC simulation time: CPU = 97.022 ms, elapsed = 36.3739 ms.
Important parameter values:
start = 0 s
outputstart = 0 s
stop = 22.4 us
step = 22.4 ns
maxstep = 224 ns
ic = all
useprevic = no
skipdc = no
reltol = 100e-06
abstol(V) = 1 uV
abstol(I) = 1 pA
temp = 27 C
tnom = 27 C
tempeffects = all
errpreset = conservative_sigglobal
method = gear2only
lteratio = 10
relref = sigglobal
cmin = 0 F
gmin = 1 pS
rabsshort = 1 mOhm

Wildcard match summary:
save 8channel_top_t_ramp.I0.I7.I0.I0.C0.* nodes: 0
save 8channel_top_t_ramp.I0.I7.I0.I0.I7.C2.* nodes: 0
save 8channel_top_t_ramp.I0.I7.I0.I0.I7.C1.* nodes: 0
save 8channel_top_t_ramp.I0.I7.I0.I0.I7.C0.* nodes: 0
save 8channel_top_t_ramp.I0.I7.I0.I1.C1.* nodes: 0
save 8channel_top_t_ramp.I0.I6.I0.I0.C0.* nodes: 0
save 8channel_top_t_ramp.I0.I6.I0.I0.I7.C2.* nodes: 0
save 8channel_top_t_ramp.I0.I6.I0.I0.I7.C1.* nodes: 0
save 8channel_top_t_ramp.I0.I6.I0.I0.I7.C0.* nodes: 0
save 8channel_top_t_ramp.I0.I6.I0.I1.C1.* nodes: 0
save 8channel_top_t_ramp.I0.I5.I0.I0.C0.* nodes: 0
save 8channel_top_t_ramp.I0.I5.I0.I0.I7.C2.* nodes: 0
save 8channel_top_t_ramp.I0.I5.I0.I0.I7.C1.* nodes: 0
save 8channel_top_t_ramp.I0.I5.I0.I0.I7.C0.* nodes: 0
save 8channel_top_t_ramp.I0.I5.I0.I1.C1.* nodes: 0
save 8channel_top_t_ramp.I0.I4.I0.I0.C0.* nodes: 0
save 8channel_top_t_ramp.I0.I4.I0.I0.I7.C2.* nodes: 0
save 8channel_top_t_ramp.I0.I4.I0.I0.I7.C1.* nodes: 0
save 8channel_top_t_ramp.I0.I4.I0.I0.I7.C0.* nodes: 0
save 8channel_top_t_ramp.I0.I4.I0.I1.C1.* nodes: 0
save 8channel_top_t_ramp.I0.I3.I0.I0.C0.* nodes: 0
save 8channel_top_t_ramp.I0.I3.I0.I0.I7.C2.* nodes: 0
save 8channel_top_t_ramp.I0.I3.I0.I0.I7.C1.* nodes: 0
save 8channel_top_t_ramp.I0.I3.I0.I0.I7.C0.* nodes: 0
save 8channel_top_t_ramp.I0.I3.I0.I1.C1.* nodes: 0
save 8channel_top_t_ramp.I0.I2.I0.I0.C0.* nodes: 0
save 8channel_top_t_ramp.I0.I2.I0.I0.I7.C2.* nodes: 0
save 8channel_top_t_ramp.I0.I2.I0.I0.I7.C1.* nodes: 0
save 8channel_top_t_ramp.I0.I2.I0.I0.I7.C0.* nodes: 0
save 8channel_top_t_ramp.I0.I2.I0.I1.C1.* nodes: 0
save 8channel_top_t_ramp.I0.I1.I0.I0.C0.* nodes: 0
save 8channel_top_t_ramp.I0.I1.I0.I0.I7.C2.* nodes: 0
save 8channel_top_t_ramp.I0.I1.I0.I0.I7.C1.* nodes: 0
save 8channel_top_t_ramp.I0.I1.I0.I0.I7.C0.* nodes: 0
save 8channel_top_t_ramp.I0.I1.I0.I1.C1.* nodes: 0
save 8channel_top_t_ramp.I0.I0.I0.I0.C0.* nodes: 0
save 8channel_top_t_ramp.I0.I0.I0.I0.I7.C2.* nodes: 0
save 8channel_top_t_ramp.I0.I0.I0.I0.I7.C1.* nodes: 0
save 8channel_top_t_ramp.I0.I0.I0.I0.I7.C0.* nodes: 0
save 8channel_top_t_ramp.I0.I0.I0.I1.C1.* nodes: 0
save 8channel_top_t_ramp.I0.I10.C0.* nodes: 0
save 8channel_top_t_ramp.I0.I10.I7.C2.* nodes: 0
save 8channel_top_t_ramp.I0.I10.I7.C1.* nodes: 0
save 8channel_top_t_ramp.I0.I10.I7.C0.* nodes: 0

Output and IC/nodeset summary:
save 1189 (voltage)
others 31

tran: time = 19.65 ns (87.7 m%), step = 18.02 ps (80.4 u%)

Then it stopped, and notified me,

INFO (ADE-3069): Errors encountered during simulation. For more information, see the log files
accessible from the Simulation -> Output Log menu.

What can I do to use multi-threading properly? Because the circuit is really huge.

Regards,

Nan

Hi Everyone,

I have a very straight forward PCELL created that adds a stretch handle to a simple rectangle, however, I would like to add "boolean inclusion" for the sub-rectangles, in this case 1 inclusion.  I have included my current script below.  Any suggestions or help would be very much appreciated!

Thanks very much,

Patrick

procedure(GGLcreateViaM1M3(cv w l "dnn")
let( (rectRodObj)
;; create a rectangle on metal1 with x & y dimensions set by w & l
rectRodObj = rodCreateRect(
?name "gglVIA1m1m3"
?cvId cv
?layer list("M1" "exclude")
?width w
?length l
?origin list(0 0)
?subRectArray list(
list(
?layer list("M2" "exclude")
?width w
?length l
)
)
)

;; create a stretch handle for the width & length

rodAssignHandleToParameter(
?parameter "w"
?rodObj rectRodObj
?handleName "upperRight"
?stretchDir "X"
?updateIncrement 0.01
); rodAssignHandleToParameter

rodAssignHandleToParameter(
?parameter "l"
?rodObj rectRodObj
?handleName "upperRight"
?stretchDir "Y"
?updateIncrement 0.01
); rodAssignHandleToParameter

); let
); procedure

;; Create the PCell, the "drawing routine" is encapsulated in the
;; GGLcreateViaM1M3 function which does all the work

pcDefinePCell(
list(ddGetObj("Sombrero_OT_oriordpj") "new_exclude" "layout")
(
(w 10)
(l 10)
)
let( ((cv pcCellView))
GGLcreateViaM1M3(cv w l)
); let

)

I have in my test several expressions that depend on the outputs of matlab scripts. For instance, a figure-of-merit "FoM" is defined as:

(Power_DUT / ((2**calcVal(ENOBcal)) * VAR("Fclock"))))

where ENOBcal is defined as "Matlab script" output (calculates the effective number of bits after calibration).

The problem is that, after the simulations finish, Assembler fails to automatically evaluate these outputs in the correct order, and all the expressions dependent on matlab scripts fail. For ex. the FoM output evaluates to "eval err", and in the CIW I get the following message:

*Error* ("expt" 1 t nil ("*Error* expt: can't handle (2**nil)"))

If I press the re-evaluate button, Assembler does figure out the right evaluation order and everything evaluates correctly. However, this is not a convenient solution for e.g. when doing long Monte Carlo runs with thousands of points: in this case the re-evaluation of all points can take long (and also consume lots of CPU resources and matlab licenses). Instead, it would be ideal if the outputs for each Monte Carlo point were correctly evaluated as the points finish simulating.

Is there anyway to enforce the correct automatic evaluation of matlab-dependent expressions in Assembler?

Thanks and regards, Jorge.

P.S. I tried removing the calcVal(), but then I get the error:

*Error* ("expt" 1 t nil ("*Error* expt: can't handle (2**unbound)"))

In layout (ICADV12.3), toolbars->show selection info and then hovering over or selecting an instance shows only the InstName and CellName. Is there a way to show the xy location of the instance as well?

In my past company we used SOS to manage our databases, and all the views in the library manager had a green/red tick beside them, dependent on whether they were checked in/out.

AT my current company, we are not using version control, but I'd like to be able to use these ticks to indicate some other property. How does Cadence know  to display them, and which color to use? Is there some kind of setting/file that enables this?

Thanks :)

Hi, everyone,

     When I use liberate to characterize some standard cells, like OAI21M0R at much lower voltage 0.3V. I set  such parameter with auto-index.

set_var max_transition 1.2e-7
set_var min_transition 1.0e-8
set_var min_output_cap 1e-17

However, I get the following error reminder

.........*Error* (char_library -auto_index) : the maximum load for OAI21M1R:Z is smaller than the specified min_output_cap (5.80844e-18F <= 1e-17F). This problem might be caused by insufficient drive strength or a max_transition value that is too small.

If I increase the max_transition value, the D-flipflop cannot meet the sequential timing. Did anyone meet this question?

Hi All,

I have a top level schematic name cell_top. In cell_top I have 2 instance name cell_A and cell_B. Cell_A and cell_B are generated by innovus play and route flow which don't have any power pin. Inside of cell_A and cell_B the power net name is vdd! and vss! which inherit from vendor lib. On the cell_top, cell_A power  connect to vddl_lvt and vssd_lvt and cell_B connect to vddl_mvt and vssd_mvt. 

Layout is connected  properly but schematic can't since there is no power pin to cell_A and cell_B. I heard that we can connect it using netSet but I don't know how to to that . Can someone please help 

thanks 

Hello, My name is Pawan Somashekar. I work as an Intern in Analog Design. I want to design an op-amp using Gm over Id method. In this case initially we have to characterise NMOS and PMOS transistors for various performance metrics like transconductance efficiency, transit frequency and so on. I  successfully characterised these for an NMOS transistors but when I'm simulating a PMOS transistor I'm encountering an error as show in the attached picture. I have tried several other ways to characterise the PMOS but I was unsuccessful. Kindly please help me. Thanks in Advance.

I am new to the Cadence Forums and am not sure if this is the correct place to ask..

I am experiencing crashes every time I right click on a wave and change its color. I am using ADE L. 

Does anyone have a similar problem?  

I was trying to install and use BAG2 from github (https://github.com/ucb-art/BAG2_cds_ff_mpt/)

The given instruction asks to download the PDK  "cds_ff_mpt " (cadence generic PDK for finfet and multi-patterned technology) from cadence support site. I was unable to find it in the cadence support. Can someone let me know where to download this from?

Hi, I am running sim with extracted view, I am providing spf file through config file.

The net name in spf file is : *|NET XI449/stg1 0.00101225PF

while when I use save all option and send this net to calculator, i get following expression:v("cmos_subrate.XI449\\/stg1:F287507" ?result "tran") 

How should i define this net while using deepprobe in testbench. ( when i do save all and search *stg1* at respective hierarchy, i dont see stg1 net but stg1:* nets presents)

thank you.