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on analoglib components doesn't show in input.scs

July 5, 2019, 2:02 pm
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Hi, Officers, 

I am running the IC6.17 and after I have add the analogLib components such as 

But in the input.scs, it didn't show the independent source. 

// Design view name: schematic
simulator lang=spectre
global 0


// Cell name: abc
// View name: schematic
R0 (net2 0) resistor r=1K
simulatorOptions options reltol=1e-3 vabstol=1e-6 iabstol=1e-12 temp=27 \
tnom=27 scalem=1.0 scale=1.0 gmin=1e-12 rforce=1 maxnotes=5 maxwarns=5 \
digits=5 cols=80 pivrel=1e-3 sensfile="../psf/sens.output" \
checklimitdest=psf
tran tran stop=1n write="spectre.ic" writefinal="spectre.fc" \
annotate=status maxiters=5
finalTimeOP info what=oppoint where=rawfile
modelParameter info what=models where=rawfile
element info what=inst where=rawfile
outputParameter info what=output where=rawfile
designParamVals info what=parameters where=rawfile
primitives info what=primitives where=rawfile
subckts info what=subckts where=rawfile
saveOptions options save=allpub

Could anyone help me with it ? 

Thanks a lot. 

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Device checking output in Spectre

July 8, 2019, 1:56 am
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Hi all,

I've got a model file .scs where I've set all rules for checking the maximum voltage across each terminal of my transistors. For example, each line is like the following:

Assert_name assert sub=my_sub mod=my_mod expr=my_expr message=my_message level=warning 

Then, in ADEL I include this file in model libraries and device checking is performed when I run simualtions. To output the results, I've found

Simulatiion->options->analog->check,

where I set dochecklimit=yes, and I specify the file where I want the report to be saved in checklimitdest. 

Next are my questions:

- When I open the output file, it just displays different violations reporting the instance and the type of violation. Is It possible to have a more readable report that lists, for example, instance, violation, intant of time when violation occured, duration, and magnitude of violation? 

-in some technoligies I've noticed that the simulator displays warning messages in the CIW because it simply reads some maximum ratings in the model files of transistors (so, a file containing different asserts is not needed here). May I know how Spectre knows how to output these warning without any assert?

Hope it's all clear (unfortuantely, cannot report technolgies that are bring used).

Thank you in advance. 

Nicola 

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Layout problem when trying to see layers

July 8, 2019, 2:55 am
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When I try to zoom in order to see the layers of the device ,I tried to increase stop in options > display but it shows me a " X " fill. I tried to change properties, but I don't know exactly the properties to add, chould I modify cell properties or instance properties.

Also ,I have a warning in WIC of cadence when adding a pmos_vtl to my layout, it says that :
The Pcell super master: NCSU_TechLib_FreePDK45/pmos_vtl/layout is not a SKILL super master.
The usage of non-SKILL Pcells in Virtuoso is not a supported feature. Your help appreciated.

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Difference between S3 and T3 layers being used as deep nwell in 22FDX.

July 8, 2019, 4:42 am
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Hi,

I want to know the difference between S3 and T3 layers used in 22FDX as both of them are mention to be used for deep nwell in DRM .

Is there any specific reason for their use ..I mean when and where to use???

Thanks

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ADE Explorer spends excessive time "evaluating"

July 8, 2019, 10:34 pm
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When I kick off a multi-run simulation in ADE explorer (for example a Monte Carlo run), it regularly spends an enormous amount of time where it reports that it is "evaluating", I'm uisng a machine with 12 cores and have "max jobs" set to 8, and it is currently at 844 seconds of evaluation. The same simulation run in spectre, or as a single run in ADE explorer is able to netlist and run in <20s. What is the tool doing during this time, and how can I get it to speed up?

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Open Layout-L instead Layout-XL by default (even if phsyconfig exists)

July 8, 2019, 10:49 pm
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Hi,

I’ve noticed that when I select a layout view and right click to open it as read-only, it opens with Layout Suite XL instead of Layout L as long as a physConfig view is present.

Is this the behavior we expect?

To me it seems more natural to open a view by default with Layout L – so that we don’t take any XL licenses unless we need to. One can always go to Launch -> Layout XL if indeed he or she wants to use the Layout XL functionality.

Is it possible to setup this behaviour ?

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Plotting temperature w.r.t time( while changing temperature using dynamic parameter in transient analysis.)

July 9, 2019, 9:56 pm
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I would like to know if there is anyway to plot temperature while changing its value in dynamic parameter w.r.t time. I am aware that in spectre.log , it asserts whenever temperature is changing w.r.t time. I am interested to plot temp.

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Virtuoso_Schematic_Editor_XL License Checkout Failure IC 6.1.8

July 10, 2019, 4:44 am
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Hello,

When using Library Manager new cellview in IC 6.1.5, it first tries to checkout Virtuoso_Schematic_Editor_L, fails, and then successfully checks out Virtuoso_Schematic_Editor_XL

When using trying the same Library Manger new cellview in IC 6.1.8, it first tries to checkout Virtuoso_Schematic_Editor_L, fails, then tries to checkout Virtuoso_Schematic_Editor_XL, and fails again.

The exact error message is:

ERROR (ELI-00111) Failed to check out license 'Virtuoso_Schematic_Editor_L'.

ERROR (ELI-00111) Failed to check out license 'Virtuoso_Schematic_Editor_XL'.

(DEBASE-100019): (deLicense-5) The open operation has been cancelled because a valid license for Schematics could not be checked out.

I have verified in the license file that we fo have a Virtuoso_Schematic_Editor_XL license.

Any ideas?

Thanks.

M. D.

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Customize Extractor Form in IC6.1.7

July 11, 2019, 1:48 am
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Hi,

I am using IC6.1.7 and would like to customize the extractor form: If I set a switch, the name of the extracted view should change automatically and contain a part of the switch's name. How can I access the source code of the extractor form to implement this or is there another way?

Thanks!

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Dependent test-bench with different temperature simulation

July 11, 2019, 7:56 am
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Here is what my requirement is,

1) First test-bench is for trimming the circuit. ( only @ 27C )

2) In second test-bench, Trimming code obtained from first test bench , should be used  but at other temperature ( eg 125C)

I am using calcVal to get the trim code from first test-bench. Simulation corner is defined based on other temperature( 125C)  as it is the worst case corner for me. So whenever I am doing the simulation, the first trimming simulation is also happening at 125C, which is understandable. 

Is there a way in GUI for first test bench to always take 27C and when 2nd ( the dependent ) test-bench is running , it should run with the temperature mentioned in the corner set up.

Any help is highly appreciated.

Thanks

Abhishek

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Multicorner runs (batch mode)

July 11, 2019, 7:59 pm
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ADEXL does not release its license once the multi-corner run completes. 

Is there a way to get ADEXL to generate the netlists and runSimulation files for all corners at once but not start the actual runs. Then one can run the simulation using command-line spectre. 

Rgds

Bhavin

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DRC problem

July 13, 2019, 1:58 pm
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I couldn't find divaDRC.rul file in my NCSU_TechLib_FreePDK45 technology library, It contains just rule file for calibre (calibreDRC.rul)

Is it a normal thing not to find it?

I tried to install and integrate calibre with cadence virtuoso 617,but I couldn't. It gives me this error:

Environnement variable CALIBRE_HOME is not set.Calibre skill interface not loaded

Your help appreciated.Thank you

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Is there a way of disabling the Layout XL annotation browser highlighting?

July 14, 2019, 9:56 am
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In Layout XL, I find the annotation browser to be more of a hindrance than anything as it's continuously highlighting nets, dimming the layout etc, regarding things that I don't care about. Quite often it'll regard things as errors that aren't errors at all because it doesn't have the same knowledge of the layout as the LVS program and misinterprets things.

I'd love to be able to turn it off completely but I can't find a way.

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Trace update in VIVA with signals from AMS (analog mixed signal) simulation

July 15, 2019, 12:01 pm
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I'm seeing a strange issue where the signals from the AMS simulation are updating differently in VIVA.  All analog signals are updating or refreshing at the same latest time stamp as the irun.log, but the digital signals just stop updating at an earlier time stamp.  This is an extremely long simulation so I'd like to know if the digital signals will update once the simulation is completed.  Thanks in advance.

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Verilog coding in Cadence Virtuoso

July 16, 2019, 9:46 am
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Hello

I am using Cadence vertuoso IC6.1.5-64b

It is the first time for me to write verilog in Cadence,

I have created new cell view in one of my libraries. I selected the Verilog with HDL reading  option as you can see from the pictures I attached.

The problem is that I am unable to type in this editor ,

Thanks

Is there any setting that I must follow before I start with the Verilog coding in cadence ?

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Difference in transient simulation result between HSPICE and SPECTRE for RC oscillator

July 16, 2019, 6:53 pm
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dear forum members,

I would appreciate it if anyone could help me with the following problem.

When oscillator transient simulation is performed with HSPICE and SPECTER, oscillator settling time differs as shown below.

     

The left figure is the result of HSPICE simulation and the right figure is the result of SPECTRE simulation.
However, even if I perform SPECTRE simulation longer than HSPICE simulation, SPECTRE does not stabilize.

I wonder why the two simulation results are different.
SPECTRE simulation setup is defaults and HSPICE simulation options are as follows.
.options post=3 nomod
+ method=gear nowarn
+ accurate=1
+ measdgt=4
+ probe
Thanks
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print schematics to pdf file

July 16, 2019, 9:34 pm
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Hi,

I am using following .cdsplotinit file

Encapsulated PostScript|Encapsulated PostScript: \
        :manufacturer=Adobe: \
        :type=epsf: \
        :resolution#300: \
        :maximumPages#1: \
        :paperSize="5x5 inches" 1500 1500: \
        :paperSize="8x8 inches" 2400 2400: \
        :paperSize="Unlimited" 72000 72000:

However when I print the schematic view to pdf, the fonts of the annotated text are thick and unreadable. circuit symbols come out fine. 

Are there any standard settings to get out good quality schematic pdfs?

Thanks

Bhavin

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mdl to .measure conversion

July 17, 2019, 1:47 am
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Hi 

I need to convert following spectremdl statement into spice (.measure) format. Help needed.

export real tpCs = cross( sig=trim(sig=V(cs), from=2n, to=7n), dir='cross, thresh=(((v(cs)@ 2n) > (10*vdd/100)) ? ((100-10)*vdd/100) : 10*vdd/100)))


Thanks

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Stop process temperature corner on certain device.

July 17, 2019, 1:55 am
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Hi All,

I have an nmos device instantiated in my testbench that basically models the input stimulus to a DUT circuit. 

I would like to be able to apply process corners and temperature on my DUT but keep my input unchanged.

Is there any easy way to do this ?

FYI, This nmos was chosen from the PDK, but i could easily use a model from one of the generic cadence PDKs.

Any help would be sincerely appreciated, and thanks for your efforts in advance.

Faisal

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Custom Signal probing options in ADE-L

July 17, 2019, 2:36 am
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I can go into ADE L - Outputs - Save All and choose (save)='lvl'  and (nestlvl)='3' and this will probe all nets in the top 3 levels of the hierarchy. 

My question is : how about if I want to probe just the first 2 levels of the hierarchy but on the 3rd level of the hierarchy I want to probe all signals only in a particular instance (say xoscillator) while not saving the signals in other blocks on the same hierarchy level. 

How can I specify this via the ADE-L GUI?

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