Hello Cadence team,
I have been using cadence PVS for some time and I have noticed that PVS has the ability to show syntactical errors in the rules files. Basically, we get a red box around the rule section in Techc&Rules tab. I am looking if this is also available as a separate checker? Such that I can use it without having to invoke PVS.
Regards
Suryansh Singh
can you please give me a well described setup guide for cadence IC 06.17.700 virtuoso + MMSIM 15.10.257 + assura 615 on centos
IC6.1.7-64b.500.13
Hi all,
I wonder if there's a possibility of sending the results of a dc match simulation directly to the ADE-L outputs window. Typically, a summary of the dc match results can be seen in the output log of the simulation, but it would be really convenient to be able to see the mismatch result directly as is done with other measurements coming from stb analysis via results > Direct Plot > main form. In any case, if there's an alternative way to do so I'd be thankful if you can share it here.
Regards,
Lewis
Hi experts!!!
I have this PSpice code (it's a PWM switch model extracted from Christophe P. Basso book - ISBN: 978-0-07-150859-9) but I don't know how to use it in a virtuoso (Spectre) simulation of a DC-DC converter.
Specifically, I would like to know how to translate it to Spectre (or Spice or whatever...), create a symbol for this code and instantiate it in my testbench.
Thank you all in advance for your help!!!
community.cadence.com/.../PWMVM_5F00_PSpice.txt
I have installed PDK that support PVS (Silterra 130nm) in Cadence IC 5.1.41 but I don't have the PVS option appearing in the virtuoso layout editor. Can anyone please guide me?
Thanking you in anticipation.
Regards
hello experts,
this could be a mixture of process vendor or EDA vendor question. I'm betting my luck here.
I have some critical devices that has to be accurate and matching. Referring to my diagram, I have shown an example of two of them - transistors A (4 fingers) and B (6 fingers) where each finger has the same W/L. When I specify the transistors using only fingers (=4 or =6, with m=1) I can see that each finger doesn't match so well and I believe what's going on is that the models know that the outer fingers have "issues" due to end effects. If I layed out the transistors separately as shown on top I will indeed get a mismatch between them just as the models predict. However, I have many transistors on this bias line and my intention is to lay them out as shown on the bottom and in that case they will match very well because those end effects are far away.
In order to get my simulation working well for matching purposes, I've had to resort to e.g. using a multiplier of 4 instead of 4 fingers. that can get me perfectly matching "fingers" but then its modeling additional effects which doesn't really exist in real circuit as laid out. Is there a way to use fingers and somehow instruct the simulator or the models to ignore those end effects?
thanks,
David
Hello,
It happens with me sometimes when I work with my layout design in Virtuoso that the pointer is not coming to the point where I want to point at it, instead it goes around the targeted point with some margin. To overcome this issue I used to display setting and try to reduce the snap dimension to less value but it is not recommend setting for the technology I am using and it is annoying to when using ruler.
Thanks
Regards
Dear All,
I am new in Digital IC Designing, i want to run Star RC Extraction Simulation.
Please share tutorial or relevant helping material.
Thanks,
Waseem
Hi! I'm trying to create statistical corners for a Monte Carlo simulation where I only consider variations on a couple of instances. The Monte Carlo run goes fine and only includes mismatch from the selected instances, but the Statistical Corners created from it are ignoring this and are including mismatch from ALL the instances in my tesbench!
I can see that the Statistical Corners generated have entries like the following:
monteCarlo::param::Instances (set to: "my_test_name%/my/instance/one, /my/instance/two%Schematic%Schematic")
but the actual netlists produced don't include any "dut=" entries for the montecarlo analysis. This is in contrast to the original Monte Carlo run, where all points have netlist entries like the following:
mc1 montecarlo numruns=1 seed=123 variations=all sampling=lds \
donominal=no scalarfile="../monteCarlo/mcdata" paramfile="../monteCarlo/mcparam" saveprocessparams=no savemistmachparams=no \
dut=[my.instance.one my.instance.two] savefamilyplots=yes savedatainseparatedir=yes wfseparation=yes firstrun=96
...whan can be going wrong? This is Spectre 17.1.0.307.isr6 64bit running over ICADV12.3-64b.500.22.
Thanks and regards, Jorge.
Hi,
I'm running IC6.1.7.500.22.
I have an ADE assembler cell with multiple schematics, each of them corresponding to a specific maestro test. I have a specific block that is used in all of the tests and I'd like to know if it is possible to change this specific block by another one, in all of the tests, all at once (like a find and replace for multiple schematics). I'm assuming that the replacing block has the same symbol shape and pins of the original block.
thanks in advance.
best regards,
Hi,
I'm running IC6.1.7.500.22.
I like to know if it is possible to de-activate the popup window of the VIVA Graph tip (see image) every time I start ADE Assembler/Explorer and run a simulation. Even though I have select the Do not show this again, it keeps coming up in new sessions!
thanks in advance.
best regards,
I have design which is in cdb version. When I convert the cdb to oa version, the via(M1_M2) sizes are 0.2 for ME1 under "Enclosures" Left and Right. I want 0.08 for Right and Left in ME1. But when I change it to 0.08 it is not changing instead by default it is going back to 0.2 only. I'm using IC 6.1.7 version.
I have 3 questions related with veriloga and really appreciate your help.
// VerilogA for integer number input to address output
`include "constants.vams"
`include "disciplines.vams"
module integer2address(vdda,gnda,OutAddress);
parameter integer BusWidth=32;
parameter integer BusOn=8;
input vdda, gnda;
output [31:0] OutAddress;
electrical [31:0] OutAddress;
electrical vdda, gnda;
genvar i;
analog begin
for(i=0;i<BusWidth;i=i+1) begin
V(OutAddress[i]) <+ V(gnda);
end
// $debug("BusOn=%d",BusOn);
if (BusOn) begin
// $debug("Enter the conditional statement, BusOn=%d",BusOn);
for(i=0;i<BusOn;i=i+1) begin
V(OutAddress[i]) <+ 1.0*V(vdda);
end
end
end
endmodule
I have the above veriloga code to have BusOn as an integer for input and the OutAddress will turn on corresponding lines in DC simulation. The code works well when BusOn is not equal to 0.
Here is my 3 questions;
1. I wonder why this code above will report error when BusOn = 0. It works for BusOn=1 to 32.
2. How to display the debug or display or strobe information in Cadence? I had difficulty to enable the $strobe feature as mentioned in this pdf. (or more specifically, I cannot find where the $strobe information are reported in Cadence, neither spectre.out nor CIW)
http://www.lumerink.com/docs/VerilogA.pdf
3. I actually have access to the latest document folder but I have difficulty to identify which one is the veriloga reference document same as the link above. Below is a screenshot of the documents that is available to me. Can you tell me which folder is for veriloga reference doc?
The error reported is shown below and I try to attach the whole spectre.out file here but was not successful.
Internal error found in spectre during AHDL read-in, during hierarchy flattening, during circuit read-in.
Encountered a critical error during simulation. Please run `mmsimpack' to pack the test case (use mmsimpack -h option to get detailed usage), and submit the case via Cadence Online Support, including the package tar file and any other information that can help identify the problem.
FATAL (SPECTRE-18): Segmentation fault.
Version 18.1.0.235.isr3 64bit -- 8 Jan 2019
****ASSERTION STACK****
0x4d9d38e
0x5e535e
0x355c432570
0x4057b3d
0x4060e50
0x4057213
0x405d07b
0x410bd16
0x41449ea
0x42b9e48
0x42caf5e
0x4035512
0x18391ad
0x183b3a5
0x183383c
0x45f38e0
0x45f3b37
0x19a2890
0x45f6e1b
0x45ad676
0x45b7630
0x19b4303
0x5908da
0x5909fd
0x501a1c
0x50f47e
0x510587
0x5113e8
0x4a6219
0x355c41ed20
0x4fc945
I actually find there is a very easy way to enable the code above to output all 0 whne BusOn=0, but I just don't understand why the top code cannot give me all OutAddress=32'b0 when BusOn=0. Below are the code to enable all lines output 0 for BusOn=0. I just remove the If conditional statement. But due to the lack of debug features in Cadence for veriloga, I have difficulty to understand why this if conditional statement doesn't work for me. Appreciate your help.
// VerilogA for integer number input to address output
`include "constants.vams"
`include "disciplines.vams"
module integer2address(vdda,gnda,OutAddress);
parameter integer BusWidth=32;
parameter integer BusOn=8;
input vdda, gnda;
output [31:0] OutAddress;
electrical [31:0] OutAddress;
electrical vdda, gnda;
genvar i;
analog begin
for(i=0;i<BusWidth;i=i+1) begin
V(OutAddress[i]) <+ V(gnda);
end
end
endmodule
I'm using IC616 and IC617 with different design kits. Although I'm using similar configuration files, all works fine for some design kits but not for others. The errors I get are:
1. Library Manager is not opening automatically. I have to open it manually.
2. Custom Design Kit libraries and cells are not loaded. A folder named .ukcds5 should be created during the first opening of the DK (this folder contains a file for the cds lib definition) but this does not happen.
3. As a result, during the simulation with spectre, the following error is generated:
error found by spectre during circuit read-in. ERROR(SFE-23): "input.scs" *** is an instance of an undefined model ***"
I can solve this issue (point 3) manually as suggested in many posts in this forum (e.g. https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/36703/error-sfe-23-undefined-model-or-subcircuit-modp-and-modn-and-error-sfe-874) but the general strange behaviour remain.
Currently, the DK ST BiCMOS55 and the ST BiCMOS9MW (vers 2.5) are working properly while the IHP SG13 and the ST BiCMOS9MW (vers. 2.8a) not. Of course, I've used the same installation procedure and I've also tested the DKs with both IC617 and IC616. Do you have any idea?
Hi,
is it possible to call a Python function in the Verilog A device model for spectre which carries out some calculations? If not is it at least possible to call a C function over PLI for spectre?
Hi,
I have a kind of weird wish. Would like to make the options form for any command to appear on assistant. The current solution in CIW->Options->User preference->Display options when command starts is bit annoying since the form appears in the screen in a obstructing way.
Background: Tried setting bindkeys for desired options instead of invoking the options form. This way the number of bindkeys are growing in number to remember. If displayed in an assistant it would be elegant.
-Ramakrishnan
Hello,
Spectre displays several notifications in log file (like that, mentiooned in subject ) preventing to analyze if a particular change in setup had an effect or no.
Does exist an option that force Spectre display all warnings.
Thanks.
Hi,
With the spectre simulator I can choose multiple runs in the noise transient simulation setup. Though, since I have also some VerilogAMS blocks in my circuit, I do not find the multiple run option in the noise transient simulation setup. I am using IC6.1.7. Is there a way of doing multiple noise transient runs?
Kind regards,
Nicolas
Hello there,
Before last weekend, everything was fine. The error came with no indication. I tried to modify the cds.lib, .cdsenv and .cdsinit. The error just always there. The problem makes ADE cannot initialize the schematic information, even I load the state manually still not work. I do not know what is the problem. I check the file and file path, they are all correct. My cadence is IC 5.1.41. Thank you very much. It bothers me for almost one week.
Error (cif): 'error while processing path' cifNormalizePathSorta : /tools/cadence/Assura/AV41/lnx86/tools/assura/etc/avtech/avTech.
