I have 3 questions related with veriloga and really appreciate your help.
// VerilogA for integer number input to address output
`include "constants.vams"
`include "disciplines.vams"
module integer2address(vdda,gnda,OutAddress);
parameter integer BusWidth=32;
parameter integer BusOn=8;
input vdda, gnda;
output [31:0] OutAddress;
electrical [31:0] OutAddress;
electrical vdda, gnda;
genvar i;
analog begin
for(i=0;i<BusWidth;i=i+1) begin
V(OutAddress[i]) <+ V(gnda);
end
// $debug("BusOn=%d",BusOn);
if (BusOn) begin
// $debug("Enter the conditional statement, BusOn=%d",BusOn);
for(i=0;i<BusOn;i=i+1) begin
V(OutAddress[i]) <+ 1.0*V(vdda);
end
end
end
endmodule
I have the above veriloga code to have BusOn as an integer for input and the OutAddress will turn on corresponding lines in DC simulation. The code works well when BusOn is not equal to 0.
Here is my 3 questions;
1. I wonder why this code above will report error when BusOn = 0. It works for BusOn=1 to 32.
2. How to display the debug or display or strobe information in Cadence? I had difficulty to enable the $strobe feature as mentioned in this pdf. (or more specifically, I cannot find where the $strobe information are reported in Cadence, neither spectre.out nor CIW)
http://www.lumerink.com/docs/VerilogA.pdf
3. I actually have access to the latest document folder but I have difficulty to identify which one is the veriloga reference document same as the link above. Below is a screenshot of the documents that is available to me. Can you tell me which folder is for veriloga reference doc?
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The error reported is shown below and I try to attach the whole spectre.out file here but was not successful.
Internal error found in spectre during AHDL read-in, during hierarchy flattening, during circuit read-in.
Encountered a critical error during simulation. Please run `mmsimpack' to pack the test case (use mmsimpack -h option to get detailed usage), and submit the case via Cadence Online Support, including the package tar file and any other information that can help identify the problem.
FATAL (SPECTRE-18): Segmentation fault.
Version 18.1.0.235.isr3 64bit -- 8 Jan 2019
****ASSERTION STACK****
0x4d9d38e
0x5e535e
0x355c432570
0x4057b3d
0x4060e50
0x4057213
0x405d07b
0x410bd16
0x41449ea
0x42b9e48
0x42caf5e
0x4035512
0x18391ad
0x183b3a5
0x183383c
0x45f38e0
0x45f3b37
0x19a2890
0x45f6e1b
0x45ad676
0x45b7630
0x19b4303
0x5908da
0x5909fd
0x501a1c
0x50f47e
0x510587
0x5113e8
0x4a6219
0x355c41ed20
0x4fc945
I actually find there is a very easy way to enable the code above to output all 0 whne BusOn=0, but I just don't understand why the top code cannot give me all OutAddress=32'b0 when BusOn=0. Below are the code to enable all lines output 0 for BusOn=0. I just remove the If conditional statement. But due to the lack of debug features in Cadence for veriloga, I have difficulty to understand why this if conditional statement doesn't work for me. Appreciate your help.
// VerilogA for integer number input to address output
`include "constants.vams"
`include "disciplines.vams"
module integer2address(vdda,gnda,OutAddress);
parameter integer BusWidth=32;
parameter integer BusOn=8;
input vdda, gnda;
output [31:0] OutAddress;
electrical [31:0] OutAddress;
electrical vdda, gnda;
genvar i;
analog begin
for(i=0;i<BusWidth;i=i+1) begin
V(OutAddress[i]) <+ V(gnda);
end
end
endmodule