Hello,
when I opened layout of "A" and launched layout XL, the schematic popped was of "B". I did update connectivity reference to schematic of "A". But, the whole hierarchy of "A" is having connectivity reference pointing to the counterparts of "B".
Please let me know how to update connectivity reference hierarchically.
Please note. A and B are similar design and both are in same library
When trying to run more than 10 concurrent runs from a self-constructed OCEAN script, on the 11th run I encounter the following error:
ERROR (ASSEMBLER-3015): The number of history items for which simulations are currently running is greater than the specified maximum number of history items
Either wait for simulations to complete or choose Options > Save and increase the value in the History Entries to Save group box, and then run simulation again.
*Error* error: The number of history items for which simulations are currently running is greater than the specified maximum number of history items - nil
I tried increasing this variable using the following command, directly inside the OCEAN script:
envSetVal("adexl.simulation" "saveLastNHistoryEntries" 'int 200)
but a different error popped up:
ERROR (ASSEMBLER-2404): Cannot find a setup database entry for handle 635339.
Provide a valid database handle and try again.
What is the safest way that I can increase this variable?
Regards,
Tiago
WARNING (ASSEMBLER-11301): The values of following environment variables conflict with each other:
spectre.envOpts controlMode 'batch'
maestro.simulation interactiveA t
I'm trying to measure the output resistance of my analog block. I vary the output bias voltage a small amount and record the current for each value of the bias. I then calculate the output resistance as the inverse of the resulting current-voltage plot.
I would like to then vary the length of the transistors in my block and for each length, find the output resistance. So I currently have a corner set up that varies the length and bias voltage. However, the expression for calculating the output resistance attempts to evaluate at every point in the corner when I really need to evaluate over sections of constant length in the corner.
I can evaluate my expression using the EvalType=Sweep for a single length and this works correctly. However, if I include multiple corners, each with a different length, then the EvalType=Sweep attempts to evaluate the output resistance over all lengths, which is not correct at all.
So I'm wondering if it's possible to do this in the ADE Explorer Maestro view?
This simulation suddenly crashed and there was a line saying that "Killed by user".
I didn't kill it myself. Does this mean that someone actively killed it?
Is there any shortcut, bindkey to bring up CIW window and Library Manager quickly?
(version IC6.16-64b.101)
Is there a way to specify that schematic netlisting commands using the "si" or "ocean" commands should internally queue for a license rather than exit with an error if the appropriate license is unavailable? Based on the information in the link below it seems the answer is "no", but I just want to confirm that. We have an automated flow that runs lots of netlisting jobs using either the si or ocean commands and find that they can die due to not being able to checkout a license. Having an internal queue and timeout limit would solve this.
Source:
support.cadence.com/.../ArticleAttachmentPortal
I'm using a model library with multiple sections for different process corners, and would like to be able to flip between them with a variable in ADE-L, without resorting to ADE-XL. Is there a way I can write a model wrapper file to do this, something like...
if (case==0)
include "model.scs" section=typ
else if (case==1)
include "model.scs" section=slow
else if (case==2)
include "model.scs" section=fast
etc
Thanks,
Nick
hello experts,
wondering how can I add a couple more marker layer to identify our own custom pcell other than existing PDK layers? any quick hint or tutorial or reference would be greatly appreciated.
thanks a lot,
David
Hi All,
Which virtuoso version is more recent,
IC 6.1.7-64b or IC 6.1.7.500.17 ?
Because I have a problem in pcells, it
wont change parameter.
Best regards,
Marben
Situation:
User1 (mysefl) originally created the layout cell "test1".
User2 has the cell checked out and the DesignSync Status Browser shows the version is in edit (version: 1.2->1.3).
The Cadence Library Manager also sees this cell as checked out.
User1 cannot access the cell other than in read-only mode.
The User2 person exists but before we start trying to use that account to release the lock status, I am taking
this as an opportunity to learn how we need to solve this going forward.
Say, it's 3 am and we have a deadline and User2 no longer exists and, maybe, we cannot get hold of any admin types to change permissions on the files.
We had a shutdown this past weekend so everyone has restarted their sessions from a pool of servers
so the chance that someone got onto the same server that they last week is small.
Besides, the cadence PID would be different.
When I look in the directory where the library data is located, there is a local version of layout.oa (not a link to design sync data)
and there are not any cdslck files in the directory.
drwxrws--- 2 user1 group 4096 May 20 18:52 .
drwxrws--- 4 user1 group 4096 May 14 14:16 ..
-rw-r----- 1 user2 group 4876 May 17 15:13 data.dm
-rw-r----- 1 user2 group 28284 May 17 15:13 layout.oa
-rw-r----- 1 user2 group 38 May 17 15:12 master.tag
-rw-r----- 1 user2 group 439 May 17 15:13 thumbnail_128x128.png
From another post, Andrew Beckett mentions the clsbd daemon.
https://community.cadence.com/cadence_technology_forums/f/custom-ic-design/25778/how-to-delete-lock-files-after-cell-is-closed
I have checked and the clsbd starts when the first user on the server starts the cadence tool (in our case 'vmac &').
On my current server, the daemon shows in the process list as owned by User3.
I logged into a different server and after starting vmac, the clsbd was running and owned by User1 (myself).
I tried using clsAdminTool to remove locks through hierarchy but, as expected, the admin tool does not see any locks.
I am finding a lot of info on how to remove locks, but not so much about this circumstance where the file is locked without any lock files present.
? Q1 - Any idea on why this scenario happened, or could have happened (lib mgr shows check out but no lock files exist in layout directory).?
? Q2 - Where else does the library manager / status browser get the check out status information other than the cdslck files that are supposed to be in the layout directory.?
? Q3 - Is there a concept of "hidden locks" in Cadence tools?
Thank You,
Michael G.
Hello,
I need your help please to export my waveform results from Cadence ADE simulator to plot it in Mathlab. Is that is possible?
Thank you
Hello,
can you tell me please how to run the Modgen in Cadence Layout tool? I tried to find it from different places in my simulator but I couldn't see it. Perhaps my simulator doesn't support this tool. I am using Layout XL editor. Also, I have Layout GXL but I usually don't work with it.
Thank you
Recently, I use Cadence Liberate to characterize the standard cell. Some novel error occurs, shown as the follow
ERROR reminder:
Did anyone meet with this type error? Hope someone can help me!
Thanks a lot!
Is there a simple command to reduce the size of all the solder dots in schematic so that the schematic pic captured with "export image" look neater.
Hello,
I encountered the following problem using cadence virtuoso IC6.1.8 ISR3 with SPECTRE 18.1 ISR6.
I did an stb analysis with a global variable sweep ("temperature" and "L"). Furthermore, I created several expressions for dc gain, phase margin and so on. The expressions are evaluated fine inside assembler. If I now right click on one evaluated expression for the phase margin and select "Plot All" I get the depicted window in VIVA - but the values do not match the expression results in assembler (They are somehow mirrored regarding the sweep variable "L").
Nevertheless, if I mark multiple phase margin results in assembler and click on "Plot" I get the correct results. I also attached a picture from that at the end.
This behaviour does not happen always, but it occurred several times to me.
Regards,
Michael
Wrong plotting
correct plotting
subject says it all.
Here is the output log (spoectre.out) when I try to run a transient simulation from ADE(L) in virtuoso. I initially wrote a d_ flip flop and applied a clock to the symbol of the d_flip_flop. Why do I get the error ?
Spectre (R) Circuit Simulator
Version 18.1.0.077 64bit -- 1 Aug 2018
Copyright (C) 1989-2018 Cadence Design Systems, Inc. All rights reserved worldwide. Cadence and Spectre are registered trademarks of Cadence Design Systems, Inc. All others are the property of their respective holders.
Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.
User: root Host: seminar-OptiPlex-3050 HostID: 7F0101 PID: 19163
Memory available: 1.7836 GB physical: 4.0223 GB
Linux : Ubuntu 16.04 LTS
CPU Type: Intel(R) Core(TM) i5-7500 CPU @ 3.40GHz
Socket: Processors [Frequency]
0: 0 [800.0], 1 [800.0], 2 [800.0], 3 [3401.0]
System load averages (1min, 5min, 15min) : 9.8 %, 5.0 %, 10.2 %
Simulating `input.scs' on seminar-OptiPlex-3050 at 3:54:51 PM, Thur May 23, 2019 (process id: 19163).
Current working directory: /root/simulation/d_ff_tb/spectre/schematic/netlist
Command line:
/vlsi/cad/cadence/SPECTRE181/tools/bin/spectre -64 input.scs \
+escchars +log ../psf/spectre.out +inter=mpsc \
+mpssession=spectre1_16392_2 -format psfxl -raw ../psf \
+lqtimeout 900 -maxw 5 -maxn 5
spectre pid = 19163
Loading /vlsi/cad/cadence/SPECTRE181/tools.lnx86/cmi/lib/64bit/5.0/libinfineon_sh.so ...
Loading /vlsi/cad/cadence/SPECTRE181/tools.lnx86/cmi/lib/64bit/5.0/libphilips_o_sh.so ...
Loading /vlsi/cad/cadence/SPECTRE181/tools.lnx86/cmi/lib/64bit/5.0/libphilips_sh.so ...
Loading /vlsi/cad/cadence/SPECTRE181/tools.lnx86/cmi/lib/64bit/5.0/libsparam_sh.so ...
Loading /vlsi/cad/cadence/SPECTRE181/tools.lnx86/cmi/lib/64bit/5.0/libstmodels_sh.so ...
Reading file: /root/simulation/d_ff_tb/spectre/schematic/netlist/input.scs
Reading file: /vlsi/cad/cadence/SPECTRE181/tools.lnx86/spectre/etc/configs/mapsubckt.cfg
Reading file: /vlsi/cad/cadence/SPECTRE181/tools.lnx86/spectre/etc/configs/spectre.cfg
Reading file: /vlsi/cad/cadence/EE668/d_ff/veriloga/veriloga.va
Reading file: /vlsi/cad/cadence/SPECTRE181/tools.lnx86/spectre/etc/ahdl/constants.vams
Reading file: /vlsi/cad/cadence/SPECTRE181/tools.lnx86/spectre/etc/ahdl/disciplines.vams
Time for NDB Parsing: CPU = 68 ms, elapsed = 299.449 ms.
Time accumulated: CPU = 80 ms, elapsed = 299.452 ms.
Peak resident memory used = 91.3 Mbytes.
Error found by spectre during AHDL read-in.
ERROR (VACOMP-2353): "/vlsi/cad/cadence/EE668/d_ff/veriloga/veriloga.va", near line 29: GCC version mismatch found. The GCC installation is either corrupted or has been modified. To solve the issue, either use the GCC version that came packaged with the release, or reinstall the release.
Opening directory input.ahdlSimDB/ (775)
Opening directory input.ahdlSimDB//31cae44eca85f506acf8071b666ca921.d_ff.ahdlcmi/ (775)
Opening directory input.ahdlSimDB//31cae44eca85f506acf8071b666ca921.d_ff.ahdlcmi/Linux-64/ (775)
Error found by spectre during AHDL read-in.
ERROR (SFE-91): Error when elaborating the instance d_ff. Simulation should be terminated.
Reading link: /vlsi/cad/cadence/SPECTRE181/tools.lnx86/spectre/etc/ahdl/discipline.h
Reading link: /vlsi/cad/cadence/SPECTRE181/tools.lnx86/spectre/etc/ahdl/constants.h
Time for Elaboration: CPU = 28 ms, elapsed = 185.845 ms.
Time accumulated: CPU = 108 ms, elapsed = 485.371 ms.
Peak resident memory used = 104 Mbytes.
Aggregate audit (3:54:52 PM, Thur May 23, 2019):
Time used: CPU = 108 ms, elapsed = 486 ms, util. = 22.2%.
Time spent in licensing: elapsed = 90.2 ms, percentage of total = 18.6%.
Peak memory used = 104 Mbytes.
Simulation started at: 3:54:51 PM, Thur May 23, 2019, ended at: 3:54:52 PM, Thur May 23, 2019, with elapsed time (wall clock): 486 ms.
spectre completes with 2 errors, 0 warnings, and 0 notices.
spectre terminated prematurely due to fatal error.
Hi,
I am trying to simulate the phase noise of a clock receiver block. It is a complex block, but you can imagine as a cascade of various buffers which are biased by some other biasing blocks (which work in DC).
The operating frequency is 10 GHz.
I'm running a PSS with the following settings:
-beat frequency=10GHz
-oversample factor: none
-number of harmonics: 10
Accurancy defaults (errpreset): Conservative
All the other are left blank.
I'm running a PNOISE after with the following settings:
Sweeptype: Default
Start-Stop: 1k-10M
Maximum Sidebands: 10
Output: Voltage (and I selected the nodes to calculate the PN)
Input source: None
Noise Type: Sources
The question is: What is the method to verify that the phase noise I'm getting is accurate enough? Is there any parameter to change and confirm that results are the same?
subject says it all.
Thanks.
Fred
subject says it all.
Thanks.
Fred